Andes Workshop

How does Andes support preemptive interrupt ?
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Author:  I-Tao [ Thu Oct 19, 2017 2:21 am ]
Post subject:  How does Andes support preemptive interrupt ?

(5) Some embedded MCU such as Super-H has 16 interrupt priority levels. If a user wants to have 16 priority levels, what specific methods should be applied for both hardware and software?

AndeStar V3 SPA specification supports preemptive interrupt with 4 programmable priority levels. The active interrupt with the highest priority is picked and serviced by the CPU. In case there are multiple active interrupts with same priority, the CPU will pick the interrupt with the smallest interrupt number (numerical value).
Also, an interrupt masking register and a current preemptive priority level register (the CPL field of the PSW register) are provided for SW to use to enhance the interrupt handling capability, such as implementing additional priorities.
If a user wants to have 16 priority levels, two methods are provided here for example.
- He can divide the 16 interrupt sources into 4 preemptive-priority groups. The interrupt sources in each group will have the same preemptive-priority level. For the interrupt sources within a group, the user can connect the highest priority interrupt source to the lowest numbered interrupt pin for that group in sequence in SoC design. Doing this will create a system with 16 priority levels when selecting among multiple active interrupts, while the preemptive behavior will only happens across the 4 preemptive-priority levels when an interrupt with a higher preemptive-priority level arrives after the CPU have entered an interrupt service routine of a lower preemptive-priority level.
- In addition to the 16 selection priority level, if the user also wants to have 16 preemptive priority level, he can use SW in an ISR to manipulate the interrupt masking and CPL registers to mask out lower priority interrupts and allow higher priority interrupts in the same preemptive-priority group to come in. Doing this effectively creates 4 additional preemptive levels within a preemptive-priority group.
- To mask out lower priority interrupts, use the interrupt masking register.
- To allow higher priority interrupts, use the CPL register to lower the current preemptive priority level.

For more detail, please reference to document : AndeStar_SPA_V3_UM072_V1.6.pdf

AndeStar_SPA_V3_UM072_V1.6.pdf [2.27 MiB]
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