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 Post subject: coalesable design in Andes NTC/NTM
PostPosted: Thu Dec 29, 2016 2:37 pm 
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Joined: Thu Apr 14, 2011 11:27 am
Posts: 13
explained coalesable meaning in document chapter 2.2.3 of AndeStar_SPA_V3_UM072_V1.4.pdf.

When bufferable device transfer data to bufferable device, both sides write commands will be “UN-ORDERED” transfer. other combination will be "IN-ORDERED" transfer.
Please study following description and tables. You will know.

2.2.3. Address Space Operation Ordering Requirement
In Andes memory architecture, loads and stores to different addresses from an AndesCore™ are, in most part, not ordered except for regions characterized by certain device-related address space attributes. For un-ordered loads and stores, if there is a need to enforce certain ordering between these memory operations, MSYNC instruction must be used to achieve this goal.
The following table lists the address space operation ordering requirement based on the translated address space attributes. The symbols used in this table are defined as:
< : This is a “BEFORE” relation between two operations in time or program sequence. For example, “A < B” in a program means instruction A comes earlier than instruction B in aprogram sequence.
u : This is an “UN-ORDERED” relation between two operations in time of performing their operations.


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