Andes Workshop

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 Forum: AndeSight STD   Topic: How to turn off N25 BTB in SID

Posted: Fri Feb 01, 2019 6:23 pm 

Replies: 0
Views: 38


Default BTB turn on in N25.
BTB can be turned off by following SID command.

 Forum: AndeSight STD   Topic: How to run performance meter on N8 simulator

Posted: Thu Jan 03, 2019 2:16 pm 

Replies: 0
Views: 2871


Default N8 disable performance meter in SID of Andesight. Adding following parameter can enable performance meter in SID.

 Forum: Realtime OS   Topic: float to String in Andes FreeRTOS

Posted: Wed Dec 26, 2018 4:26 pm 

Replies: 0
Views: 2517


Using library of vsprintf/sprintf in FreeRTOS may cause problem because of malloc issue. malloc in library doesn't know FreeRTOS heap/stack. we add ftoa function ( in main_blinky.c file )without vsprintf/sprintf which can convert float to string in attached project. attached picture is running result.

 Forum: Realtime OS   Topic: C++ code add on FreeRTOS

 Post subject: C++ code add on FreeRTOS
Posted: Tue Dec 26, 2017 7:20 pm 

Replies: 0
Views: 2275


crtend.c FreeRTOS programmed by C language. If C++ code wants to add in FreeRTOS, you should update steps as following. C++ code can merge into Andes FreeRTOS. 1. Makefile : add define in Makefile : C++ := $(CROSS_COMPILE)g++ add suffixes rules in Makefile: %.o: %.cpp $(TRACE_C++) $(Q)$(C++) -c -MM...

 Forum: Programming   Topic: How to lock cache in demo-cache-lock project

Posted: Wed Apr 12, 2017 4:15 pm 

Replies: 0
Views: 2576


The cache lock Scanario in demo-cache-lock are: For example, 1. set g_selfmodify = 7777777. 2. lock cache. If g_selfmodify = 7777777, it means cache lock successfully. Note:Keep the set value same. 3. unlock cache. if g_selfmodify = 8888888, it means cache unlock successfully. Implement cache lock b...

 Forum: AndeShape   Topic: nds32le-elf-gdb restore memory very slow

Posted: Wed Feb 15, 2017 4:24 pm 

Replies: 0
Views: 2437


Basically load command runs on bus mode and restore command runs on CPU mode. Because restore command is too slow, new version restore will switch to bus mode automatically if checking some condition meet. customer EVB may not meet such condition,and so restore command always run cpu mode and speed ...

 Forum: AndeSight STD   Topic: multi-core debug in Andesight

Posted: Fri Jan 13, 2017 3:44 pm 

Replies: 1
Views: 2854


How to setup core1 in Andesight ? core0: port 9900 -> burner (AICE) port 9901 -> telnet port 9902 -> GDB server port core1: port 9903 -> burner (AICE) port 9904 -> telnet port 9905 -> GDB server port ICEman connect to burner port . If port is occupied by other software, Andesight will use next port.

 Forum: AndeStar   Topic: 2 words read turn to burst-8 on axi-bus when executing lmw

Posted: Mon Jan 09, 2017 7:49 pm 

Replies: 0
Views: 2787


When Andes ISA "lmw/smw" execute on axi-bus, axi-bus will send burst-8 words. 8 words alignment may cause problem when reach IO peripheral. There are no 8 words alignment problem if executing basic load/store instruction on axi-bus. for eample, C code: u64_t mem_value64; mem_value64 = MEM6...

 Forum: Realtime OS   Topic: IVIC/EVIC mode setup in eCos

Posted: Tue Jan 03, 2017 12:23 pm 

Replies: 0
Views: 2837


There are 2 interrupts mode "IVIC/EVIC" in Andes core N10,D10 and N13.
The interrupt mode of default eCos demo program set IVIC mode. If your EVB netlist is EVIC mode, you have to setup eCos configuration tools as following picture. For example, N1337 EVIC mode:

 Forum: AndeStar   Topic: coalesable design in Andes NTC/NTM

Posted: Thu Dec 29, 2016 2:37 pm 

Replies: 0
Views: 2621


explained coalesable meaning in document chapter 2.2.3 of AndeStar_SPA_V3_UM072_V1.4.pdf. When bufferable device transfer data to bufferable device, both sides write commands will be “UN-ORDERED” transfer. other combination will be "IN-ORDERED" transfer. Please study following description ...
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