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 Forum: AndeSight STD   Topic: CPU and BUS mode switch

 Post subject: CPU and BUS mode switch
Posted: Fri Aug 10, 2018 11:49 am 

Replies: 0
Views: 2759

In the Memory View toolbar, you can find a button to switch source as BUS or CPU. Please refer the picture below Bus_Cpu.jpg For V3 targets, specify whether to have memory contents from CPU or BUS. The CPU mode provides contents in the system or cache memory, whereas the BUS mode provides contents o...

 Forum: AndeSight STD   Topic: If Memory View shows "????????"

Posted: Wed Aug 08, 2018 8:07 pm 

Replies: 0
Views: 1929

If the memory View is showing "???????", it means that the addresses are unknown to GDB. There are 2 possible cases in which this might happen (1) There is no device, or a read error, or can not read (2) Restricted by the memory map For example, take a look at our default N8 memory map. Du...

 Forum: AndeSight STD   Topic: ROM Patching support for AndeSight v3.1.2

Posted: Mon Jul 30, 2018 5:44 pm 

Replies: 0
Views: 1861

In AndeSight, ROM patch can be applied through indirect call functions or function table mechanism.

Please take a look at the attached document and examples.
Note: Currently, Andes only provided Hardware ROM patching document, but we don't provide Hardware ROM patching IP.

 Forum: AndeSight STD   Topic: Set a breakpoint at an address after launching program

Posted: Fri Jul 27, 2018 6:20 pm 

Replies: 0
Views: 2061

Please go through the PDF file attached herewith and follow the steps mentioned in it.
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