| Author |
Message |
Forum: AndeShape Topic: AICE V1.10.12 firmware upgrade |
| I-Tao |
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Posted: Sat Jan 13, 2018 2:51 am
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Replies: 0
Views: 9615
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Forum: AndesCore Topic: How to disable DLM ? |
| I-Tao |
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Posted: Wed Dec 20, 2017 7:33 am
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Replies: 0
Views: 14938
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| To disable DLM, it depends on what program you used. 1. If you used assembly code : pleae look for "init_dlm:" section and you should see the following : init_dlm: la $r0, .rodata ori $r0, $r0, 1 ---> change it to "0" mtsr $r0, $DLMB isb 2. If you are using c program , you should... |
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Forum: AndeStar Topic: How does Andes support preemptive interrupt ? |
| I-Tao |
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Posted: Thu Oct 19, 2017 2:21 am
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Replies: 0
Views: 25916
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| (5) Some embedded MCU such as Super-H has 16 interrupt priority levels. If a user wants to have 16 priority levels, what specific methods should be applied for both hardware and software? AndeStar V3 SPA specification supports preemptive interrupt with 4 programmable priority levels. The active inte... |
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Forum: AndeSight STD Topic: How to do the ROM patching ? and is there any examples ? |
| I-Tao |
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Posted: Fri Sep 22, 2017 5:55 am
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Replies: 0
Views: 18058
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Please take a look at the attached document and examples.
Note: Currently, Andes only provided Hardware ROM patching document, but we don't provide Hardware ROM patching IP. |
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