demo-int-new-ivbase/.cproject 0000644 0 0 45511 12415636515 14274 0 ustar 00nobody nobody
demo-int-new-ivbase/.project 0000644 0 0 4743 12415636514 14052 0 ustar 00nobody nobody
demo-int-new-ivbase
org.eclipse.cdt.managedbuilder.core.genmakebuilder
clean,full,incremental,
?name?
org.eclipse.cdt.make.core.append_environment
true
org.eclipse.cdt.make.core.autoBuildTarget
all
org.eclipse.cdt.make.core.buildArguments
org.eclipse.cdt.make.core.buildCommand
make
org.eclipse.cdt.make.core.buildLocation
${workspace_loc:/demo-int-wrapper/Debug}
org.eclipse.cdt.make.core.cleanBuildTarget
clean
org.eclipse.cdt.make.core.contents
org.eclipse.cdt.make.core.activeConfigSettings
org.eclipse.cdt.make.core.enableAutoBuild
false
org.eclipse.cdt.make.core.enableCleanBuild
true
org.eclipse.cdt.make.core.enableFullBuild
true
org.eclipse.cdt.make.core.fullBuildTarget
all
org.eclipse.cdt.make.core.stopOnError
true
org.eclipse.cdt.make.core.useDefaultBuildCmd
true
org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
full,incremental,
org.eclipse.cdt.core.cnature
org.eclipse.cdt.managedbuilder.core.managedBuildNature
org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
demo-int-new-ivbase/.settings/com.andestech.ide.cdt.managedbuilder.core.TargetModelUtils.prefs 0000644 0 0 276 12415625240 30435 0 ustar 00nobody nobody #Fri Oct 10 08:38:54 CST 2014
autoBuildEnable=false
connectType=SID
eclipse.preferences.version=1
name=ADP-AG101P-4GB-N968A-S
targetURI=rse\://LOCALHOST/~target/ADP-AG101P-4GB-N968A-S
demo-int-new-ivbase/.settings/com.andestech.ide.dsf.console.core.prefs 0000644 0 0 222 12415626715 23706 0 ustar 00nobody nobody #Fri Oct 10 08:52:29 CST 2014
com.andestech.ide.dsf.console.core.model.GDBHistory={\n "historyCommands"\: []\n}
eclipse.preferences.version=1
demo-int-new-ivbase/.settings/org.eclipse.core.resources.prefs 0000644 0 0 132 12415052012 22421 0 ustar 00nobody nobody #Wed Oct 08 04:58:48 CST 2014
eclipse.preferences.version=1
encoding//src/crt0.S=UTF-8
demo-int-new-ivbase/CmdMakefile/Makefile 0000644 0 0 6630 12415051334 16170 0 ustar 00nobody nobody # build options
## platform: AG101P, AG102, AE210P
PLAT ?= AG101P
## address: 16MB, 4GB
ADDR ?= 4GB
## mode: LOAD, BURN, XIP
ifeq (AE210P,$(PLAT))
MODE ?= XIP
else
MODE ?= LOAD
endif
## feature: EX9, IFC
FEAT ?= ""
## debug: YES, NO
DEBU ?= NO
## SIMU: YES, NO
SIMU ?= NO
$(info platform: $(PLAT), address:$(ADDR), mode:$(MODE), feature:$(FEAT), SIMU:$(SIMU))
ifneq ($(filter $(PLAT), AG101P AE210P AG102),$(PLAT))
$(error Unknown PLAT "$(PLAT)" is not supported!)
endif
ifneq ($(filter $(ADDR), 4GB 16MB),$(ADDR))
$(error ADDRing mode "$(ADDR)" is not supported!)
endif
ifeq (LOAD,$(MODE))
OPT_LLINIT := n
OPT_REMAP := n
else
ifeq (BURN,$(MODE))
OPT_LLINIT := y
OPT_REMAP := y
else
ifeq (XIP,$(MODE))
OPT_LLINIT := y
OPT_REMAP := n
else
$(error MODE "$(MODE)" is not supported!)
endif
endif
endif
ifeq (YES,$(SIMU))
OPT_LLINIT := y
OPT_REMAP := n
ifeq (XIP,$(MODE))
$(error MODE "$(MODE)" + "SIMU" is not supported!)
endif
endif
# Platform configure check
ifeq (AE210P,$(PLAT))
ifneq (XIP,$(MODE))
$(error AE210P + MODE "$(MODE)" is not supported!)
endif
endif
ifeq (AG102,$(PLAT))
ifneq (4GB,$(ADDR))
$(error AG102 + ADDR "$(ADDR)" is not supported!)
endif
endif
# tool-chain
CROSS_COMPILE ?= nds32le-elf-
CC = $(CROSS_COMPILE)gcc
OBJCOPY = $(CROSS_COMPILE)objcopy
OBJDUMP = $(CROSS_COMPILE)objdump
NM = $(CROSS_COMPILE)nm
LD_PATH = ../
SRC_PATH = ../src/
EXTENSION = -int
OBJS := \
crt0.o \
init-default.o \
init-soc.o \
interrupt.o \
main.o \
uart.o \
LDSCRIPT = $(LD_PATH)nds32.ld
#CEXTFLAGS =
#CEXTLDFLAGS =
AFLAGS = -D__ASSEMBLY__
CFLAGS = -g3 -Os -c $(CEXTFLAGS) -Wall -DCFG_MAKEFILE -DCFG_$(PLAT)
LDFLAGS = -Os -nostartfiles -static -T $(LDSCRIPT) -Wl,-Map,link.map -mrelax
OBJCOPYFLAGS = -O binary -R .note -R .comment -S
NMFLAGS = -B -n
TARGET = demo$(EXTENSION)
# feature check
ifeq ($(shell echo | $(CC) -E -dM - | grep '\<__NDS32_EXT_EX9__\>' > /dev/null && echo "EX9"), EX9)
ifeq (EX9,$(findstring EX9,$(FEAT)))
CEXTLDFLAGS += -Wl,--mex9
else
CEXTLDFLAGS += -Wl,--mno-ex9
CFLAGS += -DCONFIG_NO_NDS32_EXT_EX9
endif
else
CFLAGS += -DCONFIG_NO_NDS32_EXT_EX9
ifeq (EX9,$(findstring EX9,$(FEAT)))
$(error FEATURE "EX9" is not supported by "$(CC)"!)
endif
endif
# simulator
ifeq (YES,$(SIMU))
CFLAGS += -DCFG_SIMU
endif
# others
ifeq (y,$(OPT_LLINIT))
CFLAGS += -DCFG_LLINIT
endif
ifeq (y,$(OPT_REMAP))
CFLAGS += -DCFG_REMAP
endif
ifeq (16MB,$(ADDR))
CFLAGS += -DCFG_16MB
endif
# linker script
ifeq (AE210P,$(PLAT))
LDSCRIPT = $(LD_PATH)nds32-ae210p.ld
else
ifeq (XIP,$(MODE))
LDSCRIPT := $(LDSCRIPT:.ld=)-xip.ld
endif
ifeq (16MB,$(ADDR))
LDSCRIPT := $(LDSCRIPT:.ld=)-16mb.ld
endif
endif
# debug support
ifeq (YES,$(DEBU))
CFLAGS := $(subst -g3 -Os,-g -O0,$(CFLAGS))
LDFLAGS := $(subst -Os,-O0,$(LDFLAGS))
CFLAGS += -DCFG_DEBUG
endif
all: $(TARGET).elf
%.d: $(SRC_PATH)%.c
$(CC) $(CFLAGS) -o $@ -MM $<
%.d: $(SRC_PATH)%.S
$(CC) $(AFLAGS) $(CFLAGS) -o $@ -MM $<
%.o: $(SRC_PATH)%.c %.d
$(CC) $(CFLAGS) -o $@ $<
%.o: $(SRC_PATH)%.S %.d
$(CC) $(AFLAGS) $(CFLAGS) -o $@ $<
$(TARGET).elf: $(OBJS)
$(CC) $(LDFLAGS) $(OBJS) $(CEXTLDFLAGS) -o $(TARGET).elf $(LIB_VECTOR)
$(OBJDUMP) -D $(TARGET).elf > $(TARGET).s
$(OBJCOPY) $(OBJCOPYFLAGS) $(TARGET).elf $(TARGET).bin
$(NM) $(NMFLAGS) $(TARGET).elf > $(TARGET).map
ifneq "$(word 1,$(MAKECMDGOALS))" "clean"
-include $(OBJS:.o=.d)
endif
.PHONY: clean
clean:
rm -rf $(TARGET).* *.o *.d *.map *.out *.gcno *.gcda
demo-int-new-ivbase/Copy of nds32.ld 0000644 0 0 14336 12415051334 15203 0 ustar 00nobody nobody /* This file is generated by nds_ldsag (version 20140127). */
ENTRY(_start)
SECTIONS
{
PROVIDE (__executable_start = 0x00000000);
NDS_SAG_LMA = 0x00000000 ;
SDRAM_BEGIN = NDS_SAG_LMA;
. = 0x00000000;
_ILM_BASE = 0x00600000;
_DLM_BASE = 0x00700000;
_ILM_SIZE = 0x00010000;
_DLM_SIZE = 0x00010000;
.vector : { *(.vector) }
.nds32_init : { KEEP(*(.nds32_init)) }
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
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.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
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.rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
.rel.plt : { *(.rel.plt) }
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.init : { KEEP(*(.init)) }
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.text : { *(.text .stub .text.* .gnu.linkonce.t.*) KEEP(*(.text.*personality*)) *(.gnu.warning) . = ALIGN(4); }
.fini : { KEEP(*(.fini)) }
.ex9.itable : { *(.ex9.itable) }
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
.rodata1 : { *(.rodata1) }
.sdata2 : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }
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.eh_frame_hdr : { *(.eh_frame_hdr) }
. = ALIGN(0x20);
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.tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
. = ALIGN(32 / 8);
PROVIDE (__preinit_array_start = .);
.preinit_array : { KEEP(*(.preinit_array)) }
PROVIDE (__preinit_array_end = .);
PROVIDE (__init_array_start = .);
.init_array : { KEEP(*(.init_array)) }
PROVIDE (__init_array_end = .);
PROVIDE (__fini_array_start = .);
.fini_array : { KEEP(*(.fini_array)) }
PROVIDE (__fini_array_end = .);
.ctors : { KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o ) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) }
.dtors : { KEEP(*crtbegin*.o(.dtors)) KEEP(*(EXCLUDE_FILE (*crtend*.o ) .dtors)) KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) }
.jcr : { KEEP(*(.jcr)) }
.data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }
.dynamic : { *(.dynamic) }
.data : { *(.data .data.* .gnu.linkonce.d.*) KEEP(*(.gnu.linkonce.d.*personality*)) SORT(CONSTRUCTORS) . = ALIGN(8); }
.data1 : { *(.data1) . = ALIGN(8); }
. = ALIGN(4);
.got : { *(.got.plt) *(.got) }
.sdata_d : { *(.sdata_d .sdata_d.*) }
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.sdata_b : { *(.sdata_b .sdata_b.*) }
.sdata_f : { *(.sdata_f .sdata_f.*) }
. = ALIGN(4);
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
PROVIDE (__sbss_start = .);
PROVIDE (___sbss_start = .);
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
.sbss_f : { *(.sbss_f .sbss_f.*) *(.scommon_f .scommon_f.*) }
.sbss_b : { *(.sbss_b .sbss_b.*) *(.scommon_b .scommon_b.*) . = ALIGN(2); }
.sbss_h : { *(.sbss_h .sbss_h.*) *(.scommon_h .scommon_h.*) . = ALIGN(4); }
.sbss_w : { *(.sbss_w .sbss_w.*) *(.scommon_w .scommon_w.*) *(.dynsbss) *(.scommon) . = ALIGN(8); }
.sbss_d : { *(.sbss_d .sbss_d.*) *(.scommon_d .scommon_d.*) }
.bss : { *(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) . = ALIGN(32 / 8); }
PROVIDE (__sbss_end = .);
PROVIDE (___sbss_end = .);
. = ALIGN(32 / 8);
_end = .;
PROVIDE (end = .);
PROVIDE (_stack = 0x00800000);
SDRAM_SIZE = LOADADDR(.tbss) + SIZEOF(.tbss) - SDRAM_BEGIN;
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.note.nds32 0 : { *(.note.nds32) *(.note.nds32.*) }
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
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.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
ASSERT((DEFINED (_RELAX_END_) ? SDRAM_SIZE : 0x0) <= 0x00800000, OVERFLOW);
demo-int-new-ivbase/Copy of nds32.sag 0000644 0 0 521 12415051334 15205 0 ustar 00nobody nobody USER_SECTIONS .vector
SDRAM 0x00000000 0x00800000 ; address base 0x00000000, max_size=8M
{
EXEC 0x00000000
{
VAR _ILM_BASE = 0x00600000 ; ILM base address
VAR _DLM_BASE = 0x00700000 ; DLM base address
VAR _ILM_SIZE = 0x00010000 ; 64Kb
VAR _DLM_SIZE = 0x00010000 ; 64Kb
* (.vector)
* (+RO,+RW,+ZI)
STACK = 0x00800000
}
}
demo-int-new-ivbase/Debug/makefile 0000644 0 0 6547 12415641016 15126 0 ustar 00nobody nobody ################################################################################
# Automatically-generated file. Do not edit!
################################################################################
CYGDRIVE_C=$(shell cygpath -u "C:")
CYGDRIVE_D=$(shell cygpath -u "D:")
CYGDRIVE_E=$(shell cygpath -u "E:")
CYGDRIVE_F=$(shell cygpath -u "F:")
CYGDRIVE_H=$(shell cygpath -u "H:")
CYGDRIVE_Q=$(shell cygpath -u "Q:")
ifndef ANDESIGHT_ROOT
ANDESIGHT_ROOT=$(shell cygpath -u "C:\Andestech\AndeSight201MCU")
endif
ifndef CROSS_COMPILE
CROSS_COMPILE=nds32le-elf-
endif
ifndef SECONDARY_OUTPUT_PATH
SECONDARY_OUTPUT_PATH=output
endif
$(shell mkdir -p $(SECONDARY_OUTPUT_PATH))
-include ../makefile.init
RM := rm -rf
# All of the sources participating in the build are defined here
-include sources.mk
-include subdir.mk
-include src/subdir.mk
-include objects.mk
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(C_DEPS)),)
-include $(C_DEPS)
endif
ifneq ($(strip $(S_UPPER_DEPS)),)
-include $(S_UPPER_DEPS)
endif
endif
-include ../makefile.defs
# Add inputs and outputs from these tool invocations to the build variables
BUILD_ARTIFACT_FILE_BASE_NAME = demo-int-new-ivbase
LINKER_OUTPUTS = demo-int-new-ivbase.adx
SYMBOL_OUTPUTS += \
$(SECONDARY_OUTPUT_PATH)/symbol.txt \
READELF_OUTPUTS += \
$(SECONDARY_OUTPUT_PATH)/readelf.txt \
OBJCOPY_OUTPUTS += \
$(SECONDARY_OUTPUT_PATH)/$(BUILD_ARTIFACT_FILE_BASE_NAME).bin \
TOOL_NDS_SIZE_OUTPUT_OUTPUTS += \
.PHONY.size \
# All Target
all: demo-int-new-ivbase.adx secondary-outputs
# Tool invocations
demo-int-new-ivbase.adx: $(OBJS) $(USER_OBJS)
@echo 'Building target: $@'
@echo 'Invoking: Andes C Linker'
$(CROSS_COMPILE)gcc -O0 -nostartfiles -static -T"../nds32.ld" -o "demo-int-new-ivbase.adx" $(OBJS) $(USER_OBJS) $(LIBS)
@echo 'Finished building target: $@'
@echo ' '
$(SECONDARY_OUTPUT_PATH)/symbol.txt: $(LINKER_OUTPUTS)
@echo 'Invoking: NM (symbol listing)'
$(CROSS_COMPILE)nm -n -l -C "demo-int-new-ivbase.adx" > $(SECONDARY_OUTPUT_PATH)/symbol.txt
@echo 'Finished building: $@'
@echo ' '
$(SECONDARY_OUTPUT_PATH)/readelf.txt: $(LINKER_OUTPUTS)
@echo 'Invoking: Readelf (ELF info listing)'
$(CROSS_COMPILE)readelf -a "demo-int-new-ivbase.adx" > $(SECONDARY_OUTPUT_PATH)/readelf.txt
@echo 'Finished building: $@'
@echo ' '
: $(LINKER_OUTPUTS)
@echo 'Invoking: Objdump (disassembly)'
$(CROSS_COMPILE)objdump -x -d -C "demo-int-new-ivbase.adx" >
@echo 'Finished building: $@'
@echo ' '
$(SECONDARY_OUTPUT_PATH)/$(BUILD_ARTIFACT_FILE_BASE_NAME).bin: $(LINKER_OUTPUTS)
@echo 'Invoking: Objcopy (object content copy)'
$(CROSS_COMPILE)objcopy -S -O binary "demo-int-new-ivbase.adx" $(SECONDARY_OUTPUT_PATH)/$(BUILD_ARTIFACT_FILE_BASE_NAME).bin
@echo 'Finished building: $@'
@echo ' '
.PHONY.size: $(LINKER_OUTPUTS)
@echo 'Invoking: Size (section size listing)'
$(CROSS_COMPILE)size "demo-int-new-ivbase.adx"
@echo 'Finished building: $@'
@echo ' '
# Other Targets
clean:
-$(RM) $(TOOL_NDS_SIZE_OUTPUT_OUTPUTS)$(OBJCOPY_OUTPUTS)$(OBJS)$(C_DEPS)$(SYMBOL_OUTPUTS)$(READELF_OUTPUTS)$(EXECUTABLES)$(S_UPPER_DEPS) demo-int-new-ivbase.adx
-@echo ' '
secondary-outputs: $(SYMBOL_OUTPUTS) $(READELF_OUTPUTS) $(OBJCOPY_OUTPUTS) $(TOOL_NDS_SIZE_OUTPUT_OUTPUTS)
.PHONY: all clean dependents
.SECONDARY:
-include ../makefile.targets
demo-int-new-ivbase/Debug/objects.mk 0000644 0 0 357 12415641016 15321 0 ustar 00nobody nobody ################################################################################
# Automatically-generated file. Do not edit!
################################################################################
USER_OBJS :=
LIBS :=
demo-int-new-ivbase/Debug/output/ 0000644 0 0 0 12415361626 14535 5 ustar 00nobody nobody demo-int-new-ivbase/Debug/sources.mk 0000644 0 0 1025 12415641016 15424 0 ustar 00nobody nobody ################################################################################
# Automatically-generated file. Do not edit!
################################################################################
O_SRCS :=
C_SRCS :=
S_SRCS :=
S_UPPER_SRCS :=
OBJ_SRCS :=
ASM_SRCS :=
TOOL_NDS_SIZE_OUTPUT_OUTPUTS :=
OBJCOPY_OUTPUTS :=
OBJS :=
C_DEPS :=
SYMBOL_OUTPUTS :=
READELF_OUTPUTS :=
EXECUTABLES :=
S_UPPER_DEPS :=
# Every subdirectory with source files must be described here
SUBDIRS := \
src \
demo-int-new-ivbase/Debug/src/subdir.mk 0000644 0 0 2413 12415641016 16022 0 ustar 00nobody nobody ################################################################################
# Automatically-generated file. Do not edit!
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
C_SRCS += \
../src/init-default.c \
../src/init-soc.c \
../src/interrupt.c \
../src/main.c \
../src/uart.c
S_UPPER_SRCS += \
../src/crt0.S
OBJS += \
./src/crt0.o \
./src/init-default.o \
./src/init-soc.o \
./src/interrupt.o \
./src/main.o \
./src/uart.o
C_DEPS += \
./src/init-default.d \
./src/init-soc.d \
./src/interrupt.d \
./src/main.d \
./src/uart.d
S_UPPER_DEPS += \
./src/crt0.d
# Each subdirectory must supply rules for building sources it contributes
src/crt0.o: ../src/crt0.S
@echo 'Building file: $<'
@echo 'Invoking: Andes C Compiler'
$(CROSS_COMPILE)gcc -D__ASSEMBLY__ -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"src/crt0.d" -o "$@" "$<"
@echo 'Finished building: $<'
@echo ' '
src/%.o: ../src/%.c
@echo 'Building file: $<'
@echo 'Invoking: Andes C Compiler'
$(CROSS_COMPILE)gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
@echo 'Finished building: $<'
@echo ' '
demo-int-new-ivbase/nds32-16mb.ld 0000644 0 0 14336 12415051334 14466 0 ustar 00nobody nobody /* This file is generated by nds_ldsag (version 20140127). */
ENTRY(_start)
SECTIONS
{
PROVIDE (__executable_start = 0x00000000);
NDS_SAG_LMA = 0x00000000 ;
SDRAM_BEGIN = NDS_SAG_LMA;
. = 0x00000000;
_ILM_BASE = 0x00600000;
_DLM_BASE = 0x00700000;
_ILM_SIZE = 0x00010000;
_DLM_SIZE = 0x00010000;
.vector : { *(.vector) }
.nds32_init : { KEEP(*(.nds32_init)) }
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rel.init : { *(.rel.init) }
.rela.init : { *(.rela.init) }
.rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
.rel.fini : { *(.rel.fini) }
.rela.fini : { *(.rela.fini) }
.rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
.rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
.rel.data.rel.ro : { *(.rel.data.rel.ro*) }
.rela.data.rel.ro : { *(.rel.data.rel.ro*) }
.rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
.rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
.rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
.rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
.rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
.rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rela.dyn : { *(rela.dyn) *(.rela__libc_subfreeres) *(.rela__libc_atexit) *(.rela__libc_thread_subfreeres) *(.rela.init_array) *(.rela.fini_array) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.sdata : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
.rela.sdata : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
.rel.sbss : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
.rela.sbss : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }
.rel.sdata2 : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
.rela.sdata2 : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
.rel.sbss2 : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
.rela.sbss2 : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
.rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
.rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { KEEP(*(.init)) }
.plt : { *(.plt) }
.text : { *(.text .stub .text.* .gnu.linkonce.t.*) KEEP(*(.text.*personality*)) *(.gnu.warning) . = ALIGN(4); }
.fini : { KEEP(*(.fini)) }
.ex9.itable : { *(.ex9.itable) }
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
.rodata1 : { *(.rodata1) }
.sdata2 : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }
.sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
.eh_frame_hdr : { *(.eh_frame_hdr) }
. = ALIGN(0x20);
.eh_frame : { KEEP(*(.eh_frame)) }
.gcc_except_table : { KEEP(*(.gcc_except_table)) *(.gcc_except_table.*) }
.tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
. = ALIGN(32 / 8);
PROVIDE (__preinit_array_start = .);
.preinit_array : { KEEP(*(.preinit_array)) }
PROVIDE (__preinit_array_end = .);
PROVIDE (__init_array_start = .);
.init_array : { KEEP(*(.init_array)) }
PROVIDE (__init_array_end = .);
PROVIDE (__fini_array_start = .);
.fini_array : { KEEP(*(.fini_array)) }
PROVIDE (__fini_array_end = .);
.ctors : { KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o ) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) }
.dtors : { KEEP(*crtbegin*.o(.dtors)) KEEP(*(EXCLUDE_FILE (*crtend*.o ) .dtors)) KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) }
.jcr : { KEEP(*(.jcr)) }
.data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }
.dynamic : { *(.dynamic) }
.data : { *(.data .data.* .gnu.linkonce.d.*) KEEP(*(.gnu.linkonce.d.*personality*)) SORT(CONSTRUCTORS) . = ALIGN(8); }
.data1 : { *(.data1) . = ALIGN(8); }
. = ALIGN(4);
.got : { *(.got.plt) *(.got) }
.sdata_d : { *(.sdata_d .sdata_d.*) }
.sdata_w : { *(.sdata_w .sdata_w.*) }
.sdata_h : { *(.sdata_h .sdata_h.*) }
.sdata_b : { *(.sdata_b .sdata_b.*) }
.sdata_f : { *(.sdata_f .sdata_f.*) }
. = ALIGN(4);
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
PROVIDE (__sbss_start = .);
PROVIDE (___sbss_start = .);
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
.sbss_f : { *(.sbss_f .sbss_f.*) *(.scommon_f .scommon_f.*) }
.sbss_b : { *(.sbss_b .sbss_b.*) *(.scommon_b .scommon_b.*) . = ALIGN(2); }
.sbss_h : { *(.sbss_h .sbss_h.*) *(.scommon_h .scommon_h.*) . = ALIGN(4); }
.sbss_w : { *(.sbss_w .sbss_w.*) *(.scommon_w .scommon_w.*) *(.dynsbss) *(.scommon) . = ALIGN(8); }
.sbss_d : { *(.sbss_d .sbss_d.*) *(.scommon_d .scommon_d.*) }
.bss : { *(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) . = ALIGN(32 / 8); }
PROVIDE (__sbss_end = .);
PROVIDE (___sbss_end = .);
. = ALIGN(32 / 8);
_end = .;
PROVIDE (end = .);
PROVIDE (_stack = 0x00800000);
SDRAM_SIZE = LOADADDR(.tbss) + SIZEOF(.tbss) - SDRAM_BEGIN;
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.note.nds32 0 : { *(.note.nds32) *(.note.nds32.*) }
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
ASSERT((DEFINED (_RELAX_END_) ? SDRAM_SIZE : 0x0) <= 0x00800000, OVERFLOW);
demo-int-new-ivbase/nds32-16mb.sag 0000644 0 0 521 12415051334 14470 0 ustar 00nobody nobody USER_SECTIONS .vector
SDRAM 0x00000000 0x00800000 ; address base 0x00000000, max_size=8M
{
EXEC 0x00000000
{
VAR _ILM_BASE = 0x00600000 ; ILM base address
VAR _DLM_BASE = 0x00700000 ; DLM base address
VAR _ILM_SIZE = 0x00010000 ; 64Kb
VAR _DLM_SIZE = 0x00010000 ; 64Kb
* (.vector)
* (+RO,+RW,+ZI)
STACK = 0x00800000
}
}
demo-int-new-ivbase/nds32-ae210p.ld 0000644 0 0 17413 12415051334 14710 0 ustar 00nobody nobody /* This file is generated by nds_ldsag (version 20140127). */
ENTRY(_start)
SECTIONS
{
PROVIDE (__executable_start = 0x00000000);
NDS_SAG_LMA = 0x00000000 ;
EILM_BEGIN = NDS_SAG_LMA;
. = 0x00000000;
.vector : { *(.vector) }
.nds32_vector : { KEEP(*(.nds32_vector)) KEEP(*(SORT(.nds32_vector.*))) }
.nds32_nmih : { *(.nds32_nmih) }
.nds32_wrh : { *(.nds32_wrh) }
.nds32_jmptbl : { KEEP(*(.nds32_jmptbl)) KEEP(*(SORT(.nds32_jmptbl.*))) }
.nds32_isr : { *(.nds32_isr) }
.nds32_init : { KEEP(*(.nds32_init)) }
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rel.init : { *(.rel.init) }
.rela.init : { *(.rela.init) }
.rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
.rel.fini : { *(.rel.fini) }
.rela.fini : { *(.rela.fini) }
.rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
.rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
.rel.data.rel.ro : { *(.rel.data.rel.ro*) }
.rela.data.rel.ro : { *(.rel.data.rel.ro*) }
.rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
.rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
.rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
.rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
.rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
.rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rela.dyn : { *(rela.dyn) *(.rela__libc_subfreeres) *(.rela__libc_atexit) *(.rela__libc_thread_subfreeres) *(.rela.init_array) *(.rela.fini_array) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.sdata : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
.rela.sdata : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
.rel.sbss : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
.rela.sbss : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }
.rel.sdata2 : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
.rela.sdata2 : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
.rel.sbss2 : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
.rela.sbss2 : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
.rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
.rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { KEEP(*(.init)) }
.plt : { *(.plt) }
.text : { *(.text .stub .text.* .gnu.linkonce.t.*) KEEP(*(.text.*personality*)) *(.gnu.warning) . = ALIGN(4); }
.fini : { KEEP(*(.fini)) }
.ex9.itable : { *(.ex9.itable) }
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
.rodata1 : { *(.rodata1) }
.sdata2 : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }
.sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
.eh_frame_hdr : { *(.eh_frame_hdr) }
. = 0x00200000;
EDLM_BEGIN = .;
__data_lmastart = LOADADDR (.eh_frame_hdr) + SIZEOF (.eh_frame_hdr);
__data_start = .;
. = ALIGN(0x20);
.eh_frame : AT(LOADADDR (.eh_frame_hdr) + SIZEOF (.eh_frame_hdr))
{ KEEP(*(.eh_frame)) }
.gcc_except_table : AT(LOADADDR (.eh_frame) + SIZEOF (.eh_frame))
{ KEEP(*(.gcc_except_table)) *(.gcc_except_table.*) }
.tdata : AT(LOADADDR (.gcc_except_table) + SIZEOF (.gcc_except_table))
{ *(.tdata .tdata.* .gnu.linkonce.td.*) }
. = ALIGN(32 / 8);
PROVIDE (__preinit_array_start = .);
.preinit_array : AT(LOADADDR (.tdata) + SIZEOF (.tdata))
{ KEEP(*(.preinit_array)) }
PROVIDE (__preinit_array_end = .);
PROVIDE (__init_array_start = .);
.init_array : AT(LOADADDR (.preinit_array) + SIZEOF (.preinit_array))
{ KEEP(*(.init_array)) }
PROVIDE (__init_array_end = .);
PROVIDE (__fini_array_start = .);
.fini_array : AT(LOADADDR (.init_array) + SIZEOF (.init_array))
{ KEEP(*(.fini_array)) }
PROVIDE (__fini_array_end = .);
.ctors : AT(LOADADDR (.fini_array) + SIZEOF (.fini_array))
{ KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o ) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) }
.dtors : AT(LOADADDR (.ctors) + SIZEOF (.ctors))
{ KEEP(*crtbegin*.o(.dtors)) KEEP(*(EXCLUDE_FILE (*crtend*.o ) .dtors)) KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) }
.jcr : AT(LOADADDR (.dtors) + SIZEOF (.dtors))
{ KEEP(*(.jcr)) }
.data.rel.ro : AT(LOADADDR (.jcr) + SIZEOF (.jcr))
{ *(.data.rel.ro.local) *(.data.rel.ro*) }
.dynamic : AT(LOADADDR (.data.rel.ro) + SIZEOF (.data.rel.ro))
{ *(.dynamic) }
.data : AT(LOADADDR (.dynamic) + SIZEOF (.dynamic))
{ *(.data .data.* .gnu.linkonce.d.*) KEEP(*(.gnu.linkonce.d.*personality*)) SORT(CONSTRUCTORS) . = ALIGN(8); }
.data1 : AT(LOADADDR (.data) + SIZEOF (.data))
{ *(.data1) . = ALIGN(8); }
. = ALIGN(4);
.got : AT(LOADADDR (.data1) + SIZEOF (.data1))
{ *(.got.plt) *(.got) }
.sdata_d : AT(LOADADDR (.got) + SIZEOF (.got))
{ *(.sdata_d .sdata_d.*) }
.sdata_w : AT(LOADADDR (.sdata_d) + SIZEOF (.sdata_d))
{ *(.sdata_w .sdata_w.*) }
.sdata_h : AT(LOADADDR (.sdata_w) + SIZEOF (.sdata_w))
{ *(.sdata_h .sdata_h.*) }
.sdata_b : AT(LOADADDR (.sdata_h) + SIZEOF (.sdata_h))
{ *(.sdata_b .sdata_b.*) }
.sdata_f : AT(LOADADDR (.sdata_b) + SIZEOF (.sdata_b))
{ *(.sdata_f .sdata_f.*) }
. = ALIGN(4);
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
PROVIDE (__sbss_start = .);
PROVIDE (___sbss_start = .);
.tbss : AT(LOADADDR (.sdata_f) + SIZEOF (.sdata_f))
{ *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
.sbss_f : AT(LOADADDR (.tbss) + SIZEOF (.tbss))
{ *(.sbss_f .sbss_f.*) *(.scommon_f .scommon_f.*) }
.sbss_b : AT(LOADADDR (.sbss_f) + SIZEOF (.sbss_f))
{ *(.sbss_b .sbss_b.*) *(.scommon_b .scommon_b.*) . = ALIGN(2); }
.sbss_h : AT(LOADADDR (.sbss_b) + SIZEOF (.sbss_b))
{ *(.sbss_h .sbss_h.*) *(.scommon_h .scommon_h.*) . = ALIGN(4); }
.sbss_w : AT(LOADADDR (.sbss_h) + SIZEOF (.sbss_h))
{ *(.sbss_w .sbss_w.*) *(.scommon_w .scommon_w.*) *(.dynsbss) *(.scommon) . = ALIGN(8); }
.sbss_d : AT(LOADADDR (.sbss_w) + SIZEOF (.sbss_w))
{ *(.sbss_d .sbss_d.*) *(.scommon_d .scommon_d.*) }
.bss : AT(LOADADDR (.sbss_d) + SIZEOF (.sbss_d))
{ *(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) . = ALIGN(32 / 8); }
PROVIDE (__sbss_end = .);
PROVIDE (___sbss_end = .);
. = ALIGN(32 / 8);
_end = .;
PROVIDE (end = .);
PROVIDE (_stack = 0x00210000);
EDLM_SIZE = . - EDLM_BEGIN;
EILM_SIZE = LOADADDR(.tbss) + SIZEOF(.tbss) - EILM_BEGIN;
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.note.nds32 0 : { *(.note.nds32) *(.note.nds32.*) }
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
ASSERT((DEFINED (_RELAX_END_) ? EDLM_SIZE : 0x0) <= 0x00010000, OVERFLOW);
ASSERT((DEFINED (_RELAX_END_) ? EILM_SIZE : 0x0) <= 0x00010000, OVERFLOW);
demo-int-new-ivbase/nds32-ae210p.sag 0000644 0 0 405 12415051334 14714 0 ustar 00nobody nobody USER_SECTIONS .vector
EILM 0x00000000 0x00010000 ; address base 0x00000000, max_size=64K
{
EXEC 0x00000000
{
* (.vector)
* (+ISR,+RO)
}
EDLM 0x00200000 0x00010000
{
LOADADDR __data_lmastart
ADDR __data_start
* (+RW,+ZI)
STACK = 0x00210000
}
}
demo-int-new-ivbase/nds32-xip-16mb.ld 0000644 0 0 17172 12415051334 15265 0 ustar 00nobody nobody /* This file is generated by nds_ldsag (version 20140127). */
ENTRY(_start)
SECTIONS
{
PROVIDE (__executable_start = 0x00000000);
NDS_SAG_LMA = 0x00000000 ;
FLASH_BEGIN = NDS_SAG_LMA;
. = 0x00000000;
_ILM_BASE = 0x00600000;
_DLM_BASE = 0x00700000;
_ILM_SIZE = 0x00010000;
_DLM_SIZE = 0x00010000;
.vector : { *(.vector) }
.nds32_init : { KEEP(*(.nds32_init)) }
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rel.init : { *(.rel.init) }
.rela.init : { *(.rela.init) }
.rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
.rel.fini : { *(.rel.fini) }
.rela.fini : { *(.rela.fini) }
.rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
.rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
.rel.data.rel.ro : { *(.rel.data.rel.ro*) }
.rela.data.rel.ro : { *(.rel.data.rel.ro*) }
.rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
.rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
.rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
.rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
.rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
.rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rela.dyn : { *(rela.dyn) *(.rela__libc_subfreeres) *(.rela__libc_atexit) *(.rela__libc_thread_subfreeres) *(.rela.init_array) *(.rela.fini_array) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.sdata : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
.rela.sdata : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
.rel.sbss : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
.rela.sbss : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }
.rel.sdata2 : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
.rela.sdata2 : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
.rel.sbss2 : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
.rela.sbss2 : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
.rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
.rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { KEEP(*(.init)) }
.plt : { *(.plt) }
.text : { *(.text .stub .text.* .gnu.linkonce.t.*) KEEP(*(.text.*personality*)) *(.gnu.warning) . = ALIGN(4); }
.fini : { KEEP(*(.fini)) }
.ex9.itable : { *(.ex9.itable) }
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
.rodata1 : { *(.rodata1) }
.sdata2 : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }
.sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
.eh_frame_hdr : { *(.eh_frame_hdr) }
. = 0x00800000;
SDRAM_BEGIN = .;
__data_lmastart = LOADADDR (.eh_frame_hdr) + SIZEOF (.eh_frame_hdr);
__data_start = .;
. = ALIGN(0x20);
.eh_frame : AT(LOADADDR (.eh_frame_hdr) + SIZEOF (.eh_frame_hdr))
{ KEEP(*(.eh_frame)) }
.gcc_except_table : AT(LOADADDR (.eh_frame) + SIZEOF (.eh_frame))
{ KEEP(*(.gcc_except_table)) *(.gcc_except_table.*) }
.tdata : AT(LOADADDR (.gcc_except_table) + SIZEOF (.gcc_except_table))
{ *(.tdata .tdata.* .gnu.linkonce.td.*) }
. = ALIGN(32 / 8);
PROVIDE (__preinit_array_start = .);
.preinit_array : AT(LOADADDR (.tdata) + SIZEOF (.tdata))
{ KEEP(*(.preinit_array)) }
PROVIDE (__preinit_array_end = .);
PROVIDE (__init_array_start = .);
.init_array : AT(LOADADDR (.preinit_array) + SIZEOF (.preinit_array))
{ KEEP(*(.init_array)) }
PROVIDE (__init_array_end = .);
PROVIDE (__fini_array_start = .);
.fini_array : AT(LOADADDR (.init_array) + SIZEOF (.init_array))
{ KEEP(*(.fini_array)) }
PROVIDE (__fini_array_end = .);
.ctors : AT(LOADADDR (.fini_array) + SIZEOF (.fini_array))
{ KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o ) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) }
.dtors : AT(LOADADDR (.ctors) + SIZEOF (.ctors))
{ KEEP(*crtbegin*.o(.dtors)) KEEP(*(EXCLUDE_FILE (*crtend*.o ) .dtors)) KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) }
.jcr : AT(LOADADDR (.dtors) + SIZEOF (.dtors))
{ KEEP(*(.jcr)) }
.data.rel.ro : AT(LOADADDR (.jcr) + SIZEOF (.jcr))
{ *(.data.rel.ro.local) *(.data.rel.ro*) }
.dynamic : AT(LOADADDR (.data.rel.ro) + SIZEOF (.data.rel.ro))
{ *(.dynamic) }
.data : AT(LOADADDR (.dynamic) + SIZEOF (.dynamic))
{ *(.data .data.* .gnu.linkonce.d.*) KEEP(*(.gnu.linkonce.d.*personality*)) SORT(CONSTRUCTORS) . = ALIGN(8); }
.data1 : AT(LOADADDR (.data) + SIZEOF (.data))
{ *(.data1) . = ALIGN(8); }
. = ALIGN(4);
.got : AT(LOADADDR (.data1) + SIZEOF (.data1))
{ *(.got.plt) *(.got) }
.sdata_d : AT(LOADADDR (.got) + SIZEOF (.got))
{ *(.sdata_d .sdata_d.*) }
.sdata_w : AT(LOADADDR (.sdata_d) + SIZEOF (.sdata_d))
{ *(.sdata_w .sdata_w.*) }
.sdata_h : AT(LOADADDR (.sdata_w) + SIZEOF (.sdata_w))
{ *(.sdata_h .sdata_h.*) }
.sdata_b : AT(LOADADDR (.sdata_h) + SIZEOF (.sdata_h))
{ *(.sdata_b .sdata_b.*) }
.sdata_f : AT(LOADADDR (.sdata_b) + SIZEOF (.sdata_b))
{ *(.sdata_f .sdata_f.*) }
. = ALIGN(4);
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
PROVIDE (__sbss_start = .);
PROVIDE (___sbss_start = .);
.tbss : AT(LOADADDR (.sdata_f) + SIZEOF (.sdata_f))
{ *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
.sbss_f : AT(LOADADDR (.tbss) + SIZEOF (.tbss))
{ *(.sbss_f .sbss_f.*) *(.scommon_f .scommon_f.*) }
.sbss_b : AT(LOADADDR (.sbss_f) + SIZEOF (.sbss_f))
{ *(.sbss_b .sbss_b.*) *(.scommon_b .scommon_b.*) . = ALIGN(2); }
.sbss_h : AT(LOADADDR (.sbss_b) + SIZEOF (.sbss_b))
{ *(.sbss_h .sbss_h.*) *(.scommon_h .scommon_h.*) . = ALIGN(4); }
.sbss_w : AT(LOADADDR (.sbss_h) + SIZEOF (.sbss_h))
{ *(.sbss_w .sbss_w.*) *(.scommon_w .scommon_w.*) *(.dynsbss) *(.scommon) . = ALIGN(8); }
.sbss_d : AT(LOADADDR (.sbss_w) + SIZEOF (.sbss_w))
{ *(.sbss_d .sbss_d.*) *(.scommon_d .scommon_d.*) }
.bss : AT(LOADADDR (.sbss_d) + SIZEOF (.sbss_d))
{ *(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) . = ALIGN(32 / 8); }
PROVIDE (__sbss_end = .);
PROVIDE (___sbss_end = .);
. = ALIGN(32 / 8);
_end = .;
PROVIDE (end = .);
PROVIDE (_stack = 0x00c00000);
SDRAM_SIZE = . - SDRAM_BEGIN;
FLASH_SIZE = LOADADDR(.tbss) + SIZEOF(.tbss) - FLASH_BEGIN;
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.note.nds32 0 : { *(.note.nds32) *(.note.nds32.*) }
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
ASSERT((DEFINED (_RELAX_END_) ? SDRAM_SIZE : 0x0) <= 0x00400000, OVERFLOW);
ASSERT((DEFINED (_RELAX_END_) ? FLASH_SIZE : 0x0) <= 0x00100000, OVERFLOW);
demo-int-new-ivbase/nds32-xip-16mb.sag 0000644 0 0 651 12415051334 15272 0 ustar 00nobody nobody USER_SECTIONS .vector
FLASH 0x00000000 0x00100000 ; address base 0x00000000, max_size=1M
{
EXEC 0x00000000
{
VAR _ILM_BASE = 0x00600000 ; ILM base address
VAR _DLM_BASE = 0x00700000 ; DLM base address
VAR _ILM_SIZE = 0x00010000 ; 64Kb
VAR _DLM_SIZE = 0x00010000 ; 64Kb
* (.vector)
* (+RO)
}
SDRAM 0x00800000 0x00400000
{
LOADADDR __data_lmastart
ADDR __data_start
* (+RW,+ZI)
STACK = 0x00c00000
}
}
demo-int-new-ivbase/nds32-xip.ld 0000644 0 0 17172 12415051334 14522 0 ustar 00nobody nobody /* This file is generated by nds_ldsag (version 20140127). */
ENTRY(_start)
SECTIONS
{
PROVIDE (__executable_start = 0x00000000);
NDS_SAG_LMA = 0x00000000 ;
FLASH_BEGIN = NDS_SAG_LMA;
. = 0x00000000;
_ILM_BASE = 0x00600000;
_DLM_BASE = 0x00700000;
_ILM_SIZE = 0x00010000;
_DLM_SIZE = 0x00010000;
.vector : { *(.vector) }
.nds32_init : { KEEP(*(.nds32_init)) }
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rel.init : { *(.rel.init) }
.rela.init : { *(.rela.init) }
.rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
.rel.fini : { *(.rel.fini) }
.rela.fini : { *(.rela.fini) }
.rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
.rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
.rel.data.rel.ro : { *(.rel.data.rel.ro*) }
.rela.data.rel.ro : { *(.rel.data.rel.ro*) }
.rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
.rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
.rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
.rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
.rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
.rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rela.dyn : { *(rela.dyn) *(.rela__libc_subfreeres) *(.rela__libc_atexit) *(.rela__libc_thread_subfreeres) *(.rela.init_array) *(.rela.fini_array) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.sdata : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
.rela.sdata : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
.rel.sbss : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
.rela.sbss : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }
.rel.sdata2 : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
.rela.sdata2 : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
.rel.sbss2 : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
.rela.sbss2 : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
.rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
.rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { KEEP(*(.init)) }
.plt : { *(.plt) }
.text : { *(.text .stub .text.* .gnu.linkonce.t.*) KEEP(*(.text.*personality*)) *(.gnu.warning) . = ALIGN(4); }
.fini : { KEEP(*(.fini)) }
.ex9.itable : { *(.ex9.itable) }
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
.rodata1 : { *(.rodata1) }
.sdata2 : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }
.sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
.eh_frame_hdr : { *(.eh_frame_hdr) }
. = 0x80000000;
SDRAM_BEGIN = .;
__data_lmastart = LOADADDR (.eh_frame_hdr) + SIZEOF (.eh_frame_hdr);
__data_start = .;
. = ALIGN(0x20);
.eh_frame : AT(LOADADDR (.eh_frame_hdr) + SIZEOF (.eh_frame_hdr))
{ KEEP(*(.eh_frame)) }
.gcc_except_table : AT(LOADADDR (.eh_frame) + SIZEOF (.eh_frame))
{ KEEP(*(.gcc_except_table)) *(.gcc_except_table.*) }
.tdata : AT(LOADADDR (.gcc_except_table) + SIZEOF (.gcc_except_table))
{ *(.tdata .tdata.* .gnu.linkonce.td.*) }
. = ALIGN(32 / 8);
PROVIDE (__preinit_array_start = .);
.preinit_array : AT(LOADADDR (.tdata) + SIZEOF (.tdata))
{ KEEP(*(.preinit_array)) }
PROVIDE (__preinit_array_end = .);
PROVIDE (__init_array_start = .);
.init_array : AT(LOADADDR (.preinit_array) + SIZEOF (.preinit_array))
{ KEEP(*(.init_array)) }
PROVIDE (__init_array_end = .);
PROVIDE (__fini_array_start = .);
.fini_array : AT(LOADADDR (.init_array) + SIZEOF (.init_array))
{ KEEP(*(.fini_array)) }
PROVIDE (__fini_array_end = .);
.ctors : AT(LOADADDR (.fini_array) + SIZEOF (.fini_array))
{ KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o ) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) }
.dtors : AT(LOADADDR (.ctors) + SIZEOF (.ctors))
{ KEEP(*crtbegin*.o(.dtors)) KEEP(*(EXCLUDE_FILE (*crtend*.o ) .dtors)) KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) }
.jcr : AT(LOADADDR (.dtors) + SIZEOF (.dtors))
{ KEEP(*(.jcr)) }
.data.rel.ro : AT(LOADADDR (.jcr) + SIZEOF (.jcr))
{ *(.data.rel.ro.local) *(.data.rel.ro*) }
.dynamic : AT(LOADADDR (.data.rel.ro) + SIZEOF (.data.rel.ro))
{ *(.dynamic) }
.data : AT(LOADADDR (.dynamic) + SIZEOF (.dynamic))
{ *(.data .data.* .gnu.linkonce.d.*) KEEP(*(.gnu.linkonce.d.*personality*)) SORT(CONSTRUCTORS) . = ALIGN(8); }
.data1 : AT(LOADADDR (.data) + SIZEOF (.data))
{ *(.data1) . = ALIGN(8); }
. = ALIGN(4);
.got : AT(LOADADDR (.data1) + SIZEOF (.data1))
{ *(.got.plt) *(.got) }
.sdata_d : AT(LOADADDR (.got) + SIZEOF (.got))
{ *(.sdata_d .sdata_d.*) }
.sdata_w : AT(LOADADDR (.sdata_d) + SIZEOF (.sdata_d))
{ *(.sdata_w .sdata_w.*) }
.sdata_h : AT(LOADADDR (.sdata_w) + SIZEOF (.sdata_w))
{ *(.sdata_h .sdata_h.*) }
.sdata_b : AT(LOADADDR (.sdata_h) + SIZEOF (.sdata_h))
{ *(.sdata_b .sdata_b.*) }
.sdata_f : AT(LOADADDR (.sdata_b) + SIZEOF (.sdata_b))
{ *(.sdata_f .sdata_f.*) }
. = ALIGN(4);
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
PROVIDE (__sbss_start = .);
PROVIDE (___sbss_start = .);
.tbss : AT(LOADADDR (.sdata_f) + SIZEOF (.sdata_f))
{ *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
.sbss_f : AT(LOADADDR (.tbss) + SIZEOF (.tbss))
{ *(.sbss_f .sbss_f.*) *(.scommon_f .scommon_f.*) }
.sbss_b : AT(LOADADDR (.sbss_f) + SIZEOF (.sbss_f))
{ *(.sbss_b .sbss_b.*) *(.scommon_b .scommon_b.*) . = ALIGN(2); }
.sbss_h : AT(LOADADDR (.sbss_b) + SIZEOF (.sbss_b))
{ *(.sbss_h .sbss_h.*) *(.scommon_h .scommon_h.*) . = ALIGN(4); }
.sbss_w : AT(LOADADDR (.sbss_h) + SIZEOF (.sbss_h))
{ *(.sbss_w .sbss_w.*) *(.scommon_w .scommon_w.*) *(.dynsbss) *(.scommon) . = ALIGN(8); }
.sbss_d : AT(LOADADDR (.sbss_w) + SIZEOF (.sbss_w))
{ *(.sbss_d .sbss_d.*) *(.scommon_d .scommon_d.*) }
.bss : AT(LOADADDR (.sbss_d) + SIZEOF (.sbss_d))
{ *(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) . = ALIGN(32 / 8); }
PROVIDE (__sbss_end = .);
PROVIDE (___sbss_end = .);
. = ALIGN(32 / 8);
_end = .;
PROVIDE (end = .);
PROVIDE (_stack = 0x80800000);
SDRAM_SIZE = . - SDRAM_BEGIN;
FLASH_SIZE = LOADADDR(.tbss) + SIZEOF(.tbss) - FLASH_BEGIN;
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.note.nds32 0 : { *(.note.nds32) *(.note.nds32.*) }
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
ASSERT((DEFINED (_RELAX_END_) ? SDRAM_SIZE : 0x0) <= 0x00800000, OVERFLOW);
ASSERT((DEFINED (_RELAX_END_) ? FLASH_SIZE : 0x0) <= 0x00100000, OVERFLOW);
demo-int-new-ivbase/nds32-xip.sag 0000644 0 0 651 12415051334 14527 0 ustar 00nobody nobody USER_SECTIONS .vector
FLASH 0x00000000 0x00100000 ; address base 0x00000000, max_size=1M
{
EXEC 0x00000000
{
VAR _ILM_BASE = 0x00600000 ; ILM base address
VAR _DLM_BASE = 0x00700000 ; DLM base address
VAR _ILM_SIZE = 0x00010000 ; 64Kb
VAR _DLM_SIZE = 0x00010000 ; 64Kb
* (.vector)
* (+RO)
}
SDRAM 0x80000000 0x00800000
{
LOADADDR __data_lmastart
ADDR __data_start
* (+RW,+ZI)
STACK = 0x80800000
}
}
demo-int-new-ivbase/nds32.ld 0000644 0 0 14677 12415630460 13736 0 ustar 00nobody nobody /* This file is generated by nds_ldsag (version 20140324). */
ENTRY(_start)
SECTIONS
{
PROVIDE (__executable_start = 0x00000000);
NDS_SAG_LMA = 0x00000000 ;
SDRAM_BEGIN = NDS_SAG_LMA;
. = 0x00000000;
_ILM_BASE = 0x00600000;
_DLM_BASE = 0x00700000;
_ILM_SIZE = 0x00010000;
_DLM_SIZE = 0x00010000;
.vector : { *(.vector) }
.nds32_init : { KEEP(*(.nds32_init)) }
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rel.init : { *(.rel.init) }
.rela.init : { *(.rela.init) }
.rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
.rel.fini : { *(.rel.fini) }
.rela.fini : { *(.rela.fini) }
.rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
.rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
.rel.data.rel.ro : { *(.rel.data.rel.ro*) }
.rela.data.rel.ro : { *(.rel.data.rel.ro*) }
.rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
.rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
.rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
.rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
.rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
.rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rela.dyn : { *(rela.dyn) *(.rela__libc_subfreeres) *(.rela__libc_atexit) *(.rela__libc_thread_subfreeres) *(.rela.init_array) *(.rela.fini_array) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.sdata : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
.rela.sdata : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
.rel.sbss : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
.rela.sbss : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }
.rel.sdata2 : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
.rela.sdata2 : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
.rel.sbss2 : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
.rela.sbss2 : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
.rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
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.ex9.itable : { *(.ex9.itable) }
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
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. = ALIGN(32 / 8);
PROVIDE (__preinit_array_start = .);
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PROVIDE (__preinit_array_end = .);
PROVIDE (__init_array_start = .);
.init_array : { KEEP(*(.init_array)) }
PROVIDE (__init_array_end = .);
PROVIDE (__fini_array_start = .);
.fini_array : { KEEP(*(.fini_array)) }
PROVIDE (__fini_array_end = .);
.ctors : { KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o ) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) }
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SDRAM_SIZE = LOADADDR(.tbss) + SIZEOF(.tbss) - SDRAM_BEGIN;
NDS_SAG_LMA = 0x000010000 ;
. = 0x000010000;
.nds32_aa : { *(.nds32_aa) }
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ASSERT((DEFINED (_RELAX_END_) ? SDRAM_SIZE : 0x0) <= 0x00800000, OVERFLOW);
demo-int-new-ivbase/nds32.sag 0000644 0 0 642 12415630206 13732 0 ustar 00nobody nobody USER_SECTIONS .vector, .nds32_aa
SDRAM 0x00000000 0x00800000 ; address base 0x00000000, max_size=8M
{
EXEC 0x00000000
{
VAR _ILM_BASE = 0x00600000 ; ILM base address
VAR _DLM_BASE = 0x00700000 ; DLM base address
VAR _ILM_SIZE = 0x00010000 ; 64Kb
VAR _DLM_SIZE = 0x00010000 ; 64Kb
* (.vector)
* (+RO,+RW,+ZI)
STACK = 0x00800000
}
}
QUICKSRAM 0x000010000
{
QEXEC 0x000010000
{
* (.nds32_aa)
}
}
demo-int-new-ivbase/src/ae210p.h 0000644 0 0 33214 12415051334 14375 0 ustar 00nobody nobody #ifndef AE210P_REGS
#define AE210P_REGS
/* Check to see if this file has been included already. */
#ifndef __ASSEMBLY__
#include
#endif
/* System Clock */
#define MHz 1000000
#define CPUFREQ (40 * MHz)
#define HCLKFREQ CPUFREQ
#define PCLKFREQ CPUFREQ
#define UCLKFREQ (20 * MHz)
/* External memory mapping */
#define EILM_BASE 0x00000000
#define EDLM_BASE 0x00200000
#define ORIG_RAM_BASE EDLM_BASE
/************************************
* TARGET UART CONSTANTS *
************************************/
#define UART1_BASE 0x00F02000
#define UART2_BASE 0x00F03000
#define UART_BASE UART2_BASE
#define UART_IDREV_OFFSET 0x00
#define UART_HWCFGR_OFFSET 0x10
#define UART_OSCR_OFFSET 0x14
#define UART_RBR_OFFSET 0x20 /* Receiver Buffer Register for Read */
#define UART_THR_OFFSET 0x20 /* Transmitter Holding Register for Write */
#define UART_IER_OFFSET 0x24 /* Interrupt Enable Register */
/* Baud-Rate Divisor Latch (DL, Offset: 0x20, 0x24 when DLAB = 1) */
#define UART_DLL_OFFSET 0x20
#define UART_DLM_OFFSET 0x24
#define UART_IIR_OFFSET 0x28 /* Interrupt Identification Register */
#define UART_FCR_OFFSET 0x28 /* FIFO Control Register */
#define UART_LCR_OFFSET 0x2C /* Line Control Register */
#define UART_MCR_OFFSET 0x30 /* Modem Control Register */
#define UART_LSR_OFFSET 0x34 /* Line Status Register for Read */
#define UART_MSR_OFFSET 0x38 /* Modem Status Register */
#define UART_SPR_OFFSET 0x3C /* Scratch Pad Register */
#define UART_MDR_OFFSET 0x40 /* Mode Definition Register */
/************************************
* TARGET PIT CONSTANTS *
************************************/
#define PIT_BASE 0x00F04000
#define PIT_IDREV_OFFSET 0x00 /* Offset for PIT ID and revision register */
#define PIT_CONFIG_OFFSET 0x10 /* Offset for PIT configure register */
#define PIT_INTE_OFFSET 0x14 /* Offset for PIT interrupt enable counter */
#define PIT_INTS_OFFSET 0x18 /* Offset for PIT interrupt status counter */
#define PIT_CHNEN_OFFSET 0x1C /* Offset for PIT channel enable register */
#define PIT_CTRL_CHN(N) (0x20 + 0x10 * (N))
#define PIT_LOAD_CHN(N) (0x24 + 0x10 * (N))
#define PIT_CNTR_CHN(N) (0x28 + 0x10 * (N))
/* PIT Channel 0 ~ 3 as Timer 0 ~ 3, ATCPIT100 */
#define TM_IE (PIT_BASE + PIT_INTE_OFFSET)
#define TM_STA (PIT_BASE + PIT_INTS_OFFSET)
#define TM_CHNEN (PIT_BASE + PIT_CHNEN_OFFSET)
#define TM_CTRL(N) (PIT_BASE + PIT_CTRL_CHN(N))
#define TM_LOAD(N) (PIT_BASE + PIT_LOAD_CHN(N))
#define TM_CNTR(N) (PIT_BASE + PIT_CNTR_CHN(N))
#define TM_CTRL_32BIT (0x1 << 0)
#define TM_CTRL_PCLK (0x1 << 3)
/************************************
* TARGET GPIO CONSTANTS *
************************************/
#define GPIO_BASE 0x00F07000
#define GPIO_IDREV_OFFSET 0x00
#define GPIO_CONFIG_OFFSET 0x10
#define GPIO_DIN_OFFSET 0x20
#define GPIO_DOUT_OFFSET 0x24
#define GPIO_DIR_OFFSET 0x28
#define GPIO_DCLEAR_OFFSET 0x2C
#define GPIO_DSET_OFFSET 0x30
#define GPIO_PE_OFFSET 0x40
#define GPIO_PT_OFFSET 0x44
#define GPIO_IE_OFFSET 0x50
#define GPIO_IEMODE_OFFSET(N) (0x54 + (N) * 4)
#define GPIO_IS_OFFSET 0x64
#define GPIO_BE_OFFSET 0x70 /* BounceEnable */
#define GPIO_BC_OFFSET 0x70 /* BounceControl */
#define GPIO_USED_GCOV 0x02 /* Which GPIO to do GCOV */
#define GPIO_USED_MASK 0x7F /* Which GPIOs to use */
/************************************
* IRQ number *
************************************/
#define IRQ_RTC_PERIOD 0
#define IRQ_RTC_ALARM 1
#define IRQ_PIT 2
#define IRQ_SPI1 3
#define IRQ_SPI2 4
#define IRQ_I2C 5
#define IRQ_GPIO 6
#define IRQ_UART1 7
#define IRQ_UART2 8
#define IRQ_DMA 9
#define IRQ_BMC 10
#define IRQ_SWI 11
#define IRQ_EXTERNAL(N) (12 + (N))
#define IRQ_TIMER1 IRQ_PIT
/* interrupt sources */
#define IC_SWI (1 << IRQ_SWI)
#define IC_GPIO (1 << IRQ_GPIO)
#define IC_TIMER1 (1 << IRQ_PIT)
/* Low-level port I/O */
#define inw(reg) (*((volatile unsigned int *) (reg)))
#define outw(reg, data) ((*((volatile unsigned int *)(reg)))=(unsigned int)(data))
#ifndef NDS32_INTR_DEF
/*
* NDS32_REG_SET_BITS(addr, mask)
* Do set bits to 1 at specified location
* Operation: *addr = (*addr | mask)
*/
#define NDS32_SET_BITS(addr, mask) outw(addr, inw(addr) | mask)
/*
* NDS32_REG_WAIT4_BIT_ON(addr, mask)
* Read the contents at addr and use mask to
* mask off unused bits then wait until all of
* the remaining bits are on
*
* Operation: while(!(*addr & mask));
*/
#define NDS32_REG_WAIT4_BIT_ON(addr, mask) while(0 == (inw(addr) & mask))
/*
* NDS32_REG_WAIT4_BIT_OFF(addr, mask)
* Read the contents at addr and use mask to
* mask off unused bits then wait until all of
* the remaining bits are off
*
* Operation: while((*addr & mask));
*/
#define NDS32_REG_WAIT4_BIT_OFF(addr, mask) while(inw(addr) & mask)
/*
* NDS32_REG_WRITE(addr, data)
* Write data to specified location at addr
*
* Operation: *addr = data
* */
#define NDS32_REG_WRITE(addr, data) outw(addr, data)
/*
* NDS32_FMEMCPY_BYTE(dst, src, size)
* Do forward (low address to high address) memory copy in byte
* */
#define NDS32_FMEMCPY_BYTE(dst, src, size) \
__asm__ __volatile__( \
"sethi $r3, hi20(%2) \n\t" \
"ori $r3, $r3, lo12(%2) \n\t" \
"sethi $r1, hi20(%0) \n\t" \
"ori $r1, $r1, lo12(%0) \n\t" \
"sethi $r2, hi20(%1) \n\t" \
"ori $r2, $r2, lo12(%1) \n\t" \
"1:\n\t" \
"lbi.bi $r0, [$r2], 1 \n\t" \
"sbi.bi $r0, [$r1], 1 \n\t" \
"addi $r3, $r3, -1 \n\t" \
"bnez $r3, 1b \n\t" \
::"i"(dst),"i"(src),"i"(size):"$r0", "$r1","$r2","$r3")
#define NDS32_FMEMCPY(dst, src, size) \
__asm__ __volatile__( \
"sethi $r3, hi20(%2) \n\t" \
"ori $r3, $r3, lo12(%2) \n\t" \
"sethi $r1, hi20(%0) \n\t" \
"ori $r1, $r1, lo12(%0) \n\t" \
"sethi $r2, hi20(%1) \n\t" \
"ori $r2, $r2, lo12(%1) \n\t" \
"1:\n\t" \
"lwi.bi $r0, [$r2], 4 \n\t" \
"swi.bi $r0, [$r1], 4 \n\t" \
"addi $r3, $r3, -4 \n\t" \
"bgtz $r3, 1b \n\t" \
::"i"(dst),"i"(src),"i"(size):"$r0", "$r1","$r2","$r3")
#endif
/************************************
* HAL Level : Memory interface *
************************************/
#define HAL_MEMORY_SETUP(_base_) \
do { \
/* Enable DLM */ \
__nds32__mtsr(_base_ | 1, NDS32_SR_DLMB); \
__nds32__dsb(); \
} while(0)
#define HAL_MEMORY_REMAP()
#define HAL_MEMORY_REMAP_ADJUST()
/************************************
* HAL Level : Interrupt *
************************************/
#define HW_ISR(n) HW##n##_ISR
#define SET_HWISR(hw) HW_ISR(hw)
// ISR function name for PIT/GPIO/SWI */
#define TIMER_ISR SET_HWISR(IRQ_PIT)
#define GPIO_ISR SET_HWISR(IRQ_GPIO)
#define SWI_ISR SET_HWISR(IRQ_SWI)
// AE210P without interrupt controller
#define HAL_INTC_HWIRQ_ROUTE(_vector_, _hw_)
#define HAL_INTC_IRQ_CONFIGURE(_irqs_, _edge_, _falling_)
#define HAL_INTC_IRQ_MASK(_irqs_)
#define HAL_INTC_IRQ_UNMASK(_irqs_)
#define HAL_INTC_IRQ_CLEAR(_irqs_)
#define HAL_INTC_FIQ_CONFIGURE(_irqs_, _edge_, _falling_)
#define HAL_INTC_FIQ_MASK(_irqs_)
#define HAL_INTC_FIQ_UNMASK(_irqs_)
#define HAL_INTC_FIQ_CLEAR(_irqs_)
/************************************
* HAL Level : Timer *
************************************/
#define HAL_TIMER_INITIALIZE() \
do { \
outw(TM_CHNEN, 0x00000000); \
outw(TM_CTRL(0), TM_CTRL_32BIT | TM_CTRL_PCLK); \
outw(TM_CTRL(1), TM_CTRL_32BIT | TM_CTRL_PCLK); \
outw(TM_CTRL(2), TM_CTRL_32BIT | TM_CTRL_PCLK); \
outw(TM_CTRL(3), TM_CTRL_32BIT | TM_CTRL_PCLK); \
outw(TM_IE, 0x00000000); \
outw(TM_STA, 0xFFFFFFFF); \
} while(0)
#define HAL_TIMER_START(_tmr_) \
outw(TM_CHNEN, inw(TM_CHNEN) | (0x1 << (4 * _tmr_)))
#define HAL_TIMER_STOP(_tmr_) \
outw(TM_CHNEN, inw(TM_CHNEN) & ~(0x1 << (4 * _tmr_)))
#define HAL_TIMER_READ(_tmr_, _pvalue_) \
*(volatile unsigned int *)_pvalue_ = \
inw(TM_LOAD(_tmr_)) - inw(TM_CNTR(_tmr_))
#define HAL_TIMER_SET_PERIOD(_tmr_, _period_) \
outw(TM_LOAD(_tmr_), _period_)
#define HAL_TIMER_IRQ_ENABLE(_tmr_, _ie_) \
do { \
if(_ie_) \
outw(TM_IE, inw(TM_IE) | (0x1 << (4 * _tmr_))); \
else \
outw(TM_IE, inw(TM_IE) & ~(0x1 << (4 * _tmr_))); \
} while(0)
#define HAL_TIMER_IRQ_STATUS(_tmr_, _pvalue_) \
*(volatile unsigned int *)_pvalue_ = \
(inw(TM_STA) & (0xF << (4 * _tmr_)))
#define HAL_TIMER_IRQ_CLR(_tmr_) \
outw(TM_STA, 0xF << (4 * _tmr_))
/************************************
* HAL Level : GPIO *
************************************/
#define HAL_GPIO_INITIALIZE(_pin_) \
do { \
outw(GPIO_BASE + GPIO_DIR_OFFSET, \
inw(GPIO_BASE + GPIO_DIR_OFFSET) & ~_pin_); \
outw(GPIO_BASE + GPIO_DCLEAR_OFFSET, -1); \
outw(GPIO_BASE + GPIO_IEMODE_OFFSET(0), 0x55555555); \
outw(GPIO_BASE + GPIO_IEMODE_OFFSET(1), 0x55555555); \
outw(GPIO_BASE + GPIO_IEMODE_OFFSET(2), 0x55555555); \
outw(GPIO_BASE + GPIO_IEMODE_OFFSET(3), 0x55555555); \
outw(GPIO_BASE + GPIO_BC_OFFSET, 0x000000FF); \
outw(GPIO_BASE + GPIO_BE_OFFSET, _pin_); \
outw(GPIO_BASE + GPIO_IS_OFFSET, -1); \
outw(GPIO_BASE + GPIO_IE_OFFSET, _pin_); \
} while(0)
#define HAL_GPIO_READ() inw(GPIO_BASE + GPIO_DIN_OFFSET)
#define HAL_GPIO_IRQ_CLR(_pin_) outw(GPIO_BASE + GPIO_IS_OFFSET, _pin_)
#ifdef __ASSEMBLY__
/************************************
* HAL : AE210P defined vectors *
************************************/
.macro hal_hw_vectors
vector Interrupt_UNDEF // (9) Interrupt HW0
vector Interrupt_UNDEF // (10) Interrupt HW1
vector Interrupt_HW2 // (11) Interrupt HW2 (PIT)
vector Interrupt_UNDEF // (12) Interrupt HW3
vector Interrupt_UNDEF // (13) Interrupt HW4
vector Interrupt_UNDEF // (14) Interrupt HW5
vector Interrupt_HW6 // (15) Interrupt HW6 (GPIO)
vector Interrupt_UNDEF // (16) Interrupt HW7
vector Interrupt_UNDEF // (17) Interrupt HW8
vector Interrupt_UNDEF // (18) Interrupt HW9
vector Interrupt_UNDEF // (19) Interrupt HW10
vector Interrupt_HW11 // (20) Interrupt HW11 (SWI)
vector Interrupt_UNDEF // (21) Interrupt HW12
vector Interrupt_UNDEF // (22) Interrupt HW13
vector Interrupt_UNDEF // (23) Interrupt HW14
vector Interrupt_UNDEF // (24) Interrupt HW15
vector Interrupt_UNDEF // (25) Interrupt HW16
vector Interrupt_UNDEF // (26) Interrupt HW17
vector Interrupt_UNDEF // (27) Interrupt HW18
vector Interrupt_UNDEF // (28) Interrupt HW19
vector Interrupt_UNDEF // (29) Interrupt HW20
vector Interrupt_UNDEF // (30) Interrupt HW21
vector Interrupt_UNDEF // (31) Interrupt HW22
vector Interrupt_UNDEF // (32) Interrupt HW23
vector Interrupt_UNDEF // (33) Interrupt HW24
vector Interrupt_UNDEF // (34) Interrupt HW25
vector Interrupt_UNDEF // (35) Interrupt HW26
vector Interrupt_UNDEF // (36) Interrupt HW27
vector Interrupt_UNDEF // (37) Interrupt HW28
vector Interrupt_UNDEF // (38) Interrupt HW29
vector Interrupt_UNDEF // (39) Interrupt HW30
vector Interrupt_UNDEF // (40) Interrupt HW31
.endm
.macro hal_hw_ISR
Os_Trap_Interrupt_HW IRQ_PIT
Os_Trap_Interrupt_HW IRQ_GPIO
Os_Trap_Interrupt_HW IRQ_SWI
.endm
.macro hal_set_led, val
.endm
#endif /* __ASSEMBLY__ */
#endif /* AE210P_REGS */
demo-int-new-ivbase/src/ag101p.h 0000644 0 0 101070 12415635016 14457 0 ustar 00nobody nobody #ifndef AG101P_REGS
#define AG101P_REGS
/* Check to see if this file has been included already. */
#ifndef __ASSEMBLY__
#include
#endif
/* System Clock */
#define MHz 1000000
#ifdef CFG_16MB
#define CPUFREQ (30 * MHz)
#define HCLKFREQ (CPUFREQ / 2)
#define PCLKFREQ (CPUFREQ / 2)
#define UCLKFREQ PCLKFREQ
#else
#define CPUFREQ (60 * MHz)
#define HCLKFREQ (CPUFREQ / 2)
#define PCLKFREQ (CPUFREQ / 4)
#define UCLKFREQ PCLKFREQ
#endif
/* Different memory size defines used by SDRAM initialization */
#define SDRAM_256MB 0x0100
#define SDRAM_128MB 0x00C0
#define SDRAM_64MB 0x0040
#define SDRAM_32MB 0x0004
#define SDRAM_16MB 0x0000
#ifdef CFG_16MB
#define ORIG_RAM_BASE 0x00800000
#else
#define ORIG_RAM_BASE 0x80000000
#endif
#define REMAP_ROM_BASE ORIG_RAM_BASE
/************************************
* TARGET TIMER CONSTANTS *
************************************/
#ifdef CFG_16MB
#define TIMER_BASE 0x00F04000 /* Define base for all timer registers */
#else
#define TIMER_BASE 0x98400000 /* Define base for all timer registers */
#endif
#define TIMER_CNT_OFFSET(N) (0x00 + 0x10 * (N)) /* Offset for timer N counter register */
#define TIMER_LOAD_OFFSET(N) (0x04 + 0x10 * (N)) /* Offset for timer N load register */
#define TIMER_MATCH1_OFFSET(N) (0x08 + 0x10 * (N)) /* Offset for timer N match1 register */
#define TIMER_MATCH2_OFFSET(N) (0x0C + 0x10 * (N)) /* Offset for timer N match2 register */
#define TIMER_CNTRL_OFFSET 0x30 /* Offset for timer control register */
#define TIMER_INTS_OFFSET 0x34 /* Offset for timer interrupt status register */
#define TIMER_INTM_OFFSET 0x38 /* Offset for timer interrupt mask register */
/* Timer 1 ~ 3, ATC010 */
#define TM_CNTR(N) (TIMER_BASE + TIMER_CNT_OFFSET(N))
#define TM_LOAD(N) (TIMER_BASE + TIMER_LOAD_OFFSET(N))
#define TM_MTCH1(N) (TIMER_BASE + TIMER_MATCH1_OFFSET(N))
#define TM_MTCH2(N) (TIMER_BASE + TIMER_MATCH2_OFFSET(N))
#define TM_CR (TIMER_BASE + TIMER_CNTRL_OFFSET)
#define TM_STA (TIMER_BASE + TIMER_INTS_OFFSET)
#define TM_MSK (TIMER_BASE + TIMER_INTM_OFFSET)
/************************************
* TARGET PMU CONSTANTS *
************************************/
#ifdef CFG_16MB
#define PMUC_BASE 0x00F01000 /* Base address of PMU */
#else
#define PMUC_BASE 0x98100000 /* Base address of PMU */
#endif
#define FSSR_OFFSET 0x04 /* Frequency Scaling Status Register */
#define PWRMODE_OFFSET 0x0C /* Power Mode Register */
#define MFPSR_OFFSET 0x28 /* Multi-Function Port Setting Register */
#define PLLDLLCR0_OFFSET 0x30 /* PLL/DLL Control Register 0 */
#define SHTCR_OFFSET 0x4c /* Signal Hold Time Control Register*/
#define PLL1NS_FIELD_OFF 3 /* PLL1NS field offset */
#define PLL1NS_MASK 0x00000ff8 /* PLL1NS field mask */
#define DIV_FACTOR_FIELD_OFF 4 /* Clock dividor factor field offset */
#define DIV_FACTOR_MASK 0x000000f0 /* Clock dividor factor mask */
/************************************
* TARGET INTERRUPT CONSTANTS *
************************************/
#ifdef CFG_16MB
#define INTC_BASE 0x00F08000 /* Interrupt Controller base address */
#else
#define INTC_BASE 0x98800000 /* Interrupt Controller base address */
#endif
#define IRQSRCR_OFFSET 0x00 /* IRQ(HW1) Source Register offset */
#define IRQER_OFFSET 0x04 /* IRQ(HW1) Enable Register offset */
#define IRQICR_OFFSET 0x08 /* IRQ(HW1) Interrupt Clear Register offset */
#define IRQTMR_OFFSET 0x0C /* IRQ(HW1) Trigger Mode Register offset */
#define IRQTLR_OFFSET 0x10 /* IRQ(HW1) Trigger Level Register offset */
#define IRQSR_OFFSET 0x14 /* IRQ(HW1) Status Register offset */
#define FIQSRCR_OFFSET 0x20 /* FIQ(HW0) Source Register offset */
#define FIQER_OFFSET 0x24 /* FIQ(HW0) Enable Register offset */
#define FIQICR_OFFSET 0x28 /* FIQ(HW0) Interrupt Clear Register offset */
#define FIQTMR_OFFSET 0x2C /* FIQ(HW0) Trigger Mode Register offset */
#define FIQTLR_OFFSET 0x30 /* FIQ(HW0) Trigger Level Register offset */
#define FIQSR_OFFSET 0x34 /* FIQ(HW0) Status Register offset */
#define INT_ER_INIT 0x00000000 /* values used to disable all interrupts */
#define INT_CLEAR_VALUE 0xFFFFFFFF /* values used to clear all pending interrupts */
/* Constants utilized by interrupt handler for nesting interrupts */
#define FIRST_STACK_OFFSET 40 /* First stack offset FIQ/IRQ interrupt unnset */
#define IRQER_STACK_OFFSET 40 /* INT MASK register */
#define FIQER_STACK_OFFSET 44 /* Interrupt ER OFFSET register value */
#define MASK1_STACK_OFFSET 40 /* INT MASK register */
#define IEROFF_STACK_OFFSET 44 /* Interrupt ER OFFSET register value */
#define NUM_MASK_REGS 2 /* Number of mask register (1 mask register */
/* and base address of interrupt */
/* control register for core module) */
#define MASK_REG_SPACE (NUM_MASK_REGS * 4)
/************************************
* TARGET SMC CONSTANTS *
************************************/
#ifdef CFG_16MB
#define SMC_BASE 0x00E01000 /* Static Memory Controller base address */
#else
#define SMC_BASE 0x90200000 /* Static Memory Controller base address */
#endif
#define BANK0TPR_OFFSET 0x4 /* Bank 0 timing parameter register */
#define SMC_BANK0TPR_INIT 0x00151151 /* ? */
#ifdef CFG_16MB
#define LED_BASE (SMC_BASE+(1<<12)-4) /* LED base address */
#else
#define LED_BASE (SMC_BASE+(1<<20)-4) /* LED base address */
#endif
/************************************
* TARGET SDRAM CONSTANTS *
************************************/
#ifdef CFG_16MB
#define SDRAMC_BASE 0x00E02000 /* SDRAM Controller base address */
#else
#define SDRAMC_BASE 0x90300000 /* SDRAM Controller base address */
#endif
#define PARM1_OFFSET 0x00 /* Parameter 1 Register offset */
#define PARM2_OFFSET 0x04 /* Parameter 2 Register offset */
#define CONFIG1_OFFSET 0x08 /* Configuration 1 Register offset */
#define CONFIG2_OFFSET 0x0C /* Configuration 2 Register offset */
#define SDRAMC_PARM1_INIT 0x00011312 /* SDRAMC Parameter 1 init value */
#define SDRAMC_PARM2_INIT 0x004800a0 /* SDRAMC Parameter 2 init value */
#ifdef CFG_16MB
#define SDRAMC_CONFIG1_INIT 0x00002023 /* SDRAMC bank 0 init value */
#else
#define SDRAMC_CONFIG1_INIT 0x00002326 /* SDRAMC bank 0 init value */
#endif
#define SDRAMC_CONFIG2_INIT 0x00000010 /* SDRAM Precharge Action Bit for Configuration Register */
/************************************
* TARGET DECODER CONSTANTS *
************************************/
#ifdef CFG_16MB
#define AHBC_BASE 0x00E00000 /* AHB Controller base address */
#else
#define AHBC_BASE 0x90100000 /* AHB Controller base address */
#endif
#define DEVICE4_OFFSET 0x10 /* Device 4 Control Register offset */
#define DEVICE6_OFFSET 0x18 /* Device 6 Control Register offset */
#define INTC_OFFSET 0x88 /* Interrupt Control Register offset */
#define AHBC_DEV6_INIT 0x10080000 /* AHBC Device 6 init value */
#define AHBC_REMAP_BIT 0x00000001 /* AHBC remap bit for Interrupt Control Register */
#ifdef CFG_16MB
/* ROM */
#define AHBC_DEV4_SIZE_INIT 0x0000000b /* 1MB */
#define AHBC_DEV4_SIZE_REMAP AHBC_DEV4_SIZE_INIT
/* RAM */
#define AHBC_DEV6_SIZE_INIT 0x0000000d /* 4MB */
#define AHBC_DEV6_SIZE_REMAP 0x0000000e /* 8MB */
#else
/* ROM */
#define AHBC_DEV4_SIZE_INIT 0x00080000 /* 256MB */
#define AHBC_DEV4_SIZE_REMAP AHBC_DEV4_SIZE_INIT
/* RAM */
#define AHBC_DEV6_SIZE_INIT 0x00080000 /* 256MB */
#define AHBC_DEV6_SIZE_REMAP 0x000b0000 /* 2GB */
#endif
/************************************
* TARGET GPIO CONSTANTS *
************************************/
#ifdef CFG_16MB
#define GPIO_BASE 0x00F07000 /* GPIO base address */
#else
#define GPIO_BASE 0x98700000 /* GPIO base address */
#endif
#define GPIO_DOUT_OFFSET 0x0
#define GPIO_DIN_OFFSET 0x4
#define GPIO_DIR_OFFSET 0x8
#define GPIO_DSET_OFFSET 0x10
#define GPIO_DCLEAR_OFFSET 0x14
#define GPIO_PE_OFFSET 0x18
#define GPIO_PT_OFFSET 0x1C
#define GPIO_IE_OFFSET 0x20
#define GPIO_IS_OFFSET 0x24
#define GPIO_IT_OFFSET 0x34
#define GPIO_IC_OFFSET 0x30
#define GPIO_IB_OFFSET 0x38
#define GPIO_IR_OFFSET 0x3c
#define GPIO_BE_OFFSET 0x40 /* BounceEnable */
#define GPIO_BPS_OFFSET 0x44 /* BouncePreScale */
#define GPIO_USED_GCOV 0x01 /* Which GPIO to do GCOV */
#define GPIO_USED_MASK 0x3E /* Which GPIOs to use */
/************************************
* TARGET UART CONSTANTS *
************************************/
#ifdef CFG_16MB
#define UART_BASE 0x00F16000
#else
#define UART_BASE 0x99600000
#endif
#define UART_RBR_OFFSET 0x00 /* Receiver Buffer Register for Read */
#define UART_THR_OFFSET 0x00 /* Transmitter Holding Register for Write */
#define UART_IER_OFFSET 0x04 /* Interrupt Enable Register */
/* Baud-Rate Divisor Latch (DL, Offset: 0x00, 0x04 when DLAB = 1) */
#define UART_DLL_OFFSET 0x00
#define UART_DLM_OFFSET 0x04
#define UART_IIR_OFFSET 0x08 /* Interrupt Identification Register */
#define UART_FCR_OFFSET 0x08 /* FIFO Control Register */
/* Prescaler Register (PSR, Offset: 0x08 when DLAB =1) */
#define UART_PSR_OFFSET 0x08
#define UART_LCR_OFFSET 0x0C /* Line Control Register */
#define UART_MCR_OFFSET 0x10 /* Modem Control Register */
#define UART_LSR_OFFSET 0x14 /* Line Status Register for Read */
#define UART_TST_OFFSET 0x14 /* Testing Register for Write */
#define UART_MSR_OFFSET 0x18 /* Modem Status Register */
#define UART_SPR_OFFSET 0x1C /* Scratch Pad Register */
#define UART_MDR_OFFSET 0x20 /* Mode Definition Register */
#define UART_ACR_OFFSET 0x24 /* Auxiliary Control Register */
#define UART_TXLENL_OFFSET 0x28 /* Transmit Frame-Length Register (Low) */
#define UART_TXLENH_OFFSET 0x2C /* Transmit Frame-Length Register (High)*/
#define UART_MRXLENL_OFFSET 0x30 /* Maximum Receiver Frame-Length (Low) */
#define UART_MRXLENH_OFFSET 0x34 /* Maximum Receiver Frame-Length (High)*/
#define UART_PLR_OFFSET 0x38 /* Preamble Length Register */
#define UART_FMIIR_PIO_OFFSET 0x3C /* Interrupt Identification Register in FIR Mode (PIO mode) */
#define UART_FMIIR_DMA_OFFSET 0x3C /* Interrupt Identification Register in FIR Mode (DMA mode) */
#define UART_FMIIER_PIO_OFFSET 0x40 /* Interrupt Identification Enable Register in FIR Mode (PIO mode) */
#define UART_FMIIER_DMA_OFFSET 0x40 /* Interrupt Identification Enable Register in FIR Mode (DMA mode) */
#define UART_STFF_STS_OFFSET 0x44 /* Status FIFO Line Status Register */
#define UART_STFF_RXLENL_OFFSET 0x48 /* Status FIFO Received Frame-Length Register Low */
#define UART_STFF_RXLENH_OFFSET 0x4C /* Status FIFO Received Frame-Length Register High */
#define UART_FMLSR_OFFSET 0x50 /* Link Status Register in FIR Mode */
#define UART_FMLSIER_OFFSET 0x54 /* Link Status Interrupt Enable Register in FIR Mode */
#define UART_RSR_OFFSET 0x58 /* Resume Register */
#define UART_RXFF_CNTR_OFFSET 0x5C /* RX FIFO Count Register */
#define UART_LSTFMLENL_OFFSET 0x60 /* Last Frame Length Register Low */
#define UART_LSTFMLENH_OFFSET 0x64 /* Last Frame Length Register High */
#define UART_FEATURE_OFFSET 0x68 /* Feature Register */
#define UART_REVD1_OFFSET 0x6C /* Revision Register Digit 1 */
#define UART_REVD2_OFFSET 0x70 /* Revision Register Digit 2 */
#define UART_REVD3_OFFSET 0x74 /* Revision Register Digit 3 */
/************************************
* IRQ number *
************************************/
#define HW0_FIQ 0 // For 4GB platform only
#define HW1_IRQ 1 // For 4GB platform only
#define NEW_HW1_IRQ 1
#define HW6_SW0 6 // For 4GB platform only
#define IRQ_CFC_CD 0
#define IRQ_CFC_DMA 1
#define IRQ_SSP1 2
#define IRQ_I2C 3
#define IRQ_SDC 5
#define IRQ_SSP2 6
#define IRQ_SWI 9
#define IRQ_UART1 10
#define IRQ_UART2 11
#define IRQ_GPIO 13
#define IRQ_TIMER2 14
#define IRQ_TIMER3 15
#define IRQ_TIMER1 19
#define IRQ_APB_BRIDGE 24
#define IRQ_CPE_AHB_DMA 21
#define IRQ_CPE_APB_DMA 24
#define IRQ_MAC 25
#define IRQ_TOUCH 28
#define IRQ_EXT_A321 30
#define IRQ_USBDEV 26 // USB device
#define IRQ_FOTG200 29 // FOTG200 device
//#define IRQ_USB_HOST11 27 // USB Host 1.1
#define IRQ_SECU 29 // security AES/DES/3DES
#define IRQ_USB_HOST20 29 // USB Host 200
/* interrupt sources */
#define IC_SWI (1 << IRQ_SWI)
#define IC_GPIO (1 << IRQ_GPIO)
#define IC_TIMER1 (1 << IRQ_TIMER1)
#define IC_TIMER2 (1 << IRQ_TIMER2)
#define IC_TIMER3 (1 << IRQ_TIMER3)
/* Low-level port I/O */
#define inw(reg) (*((volatile unsigned int *) (reg)))
#define outw(reg, data) ((*((volatile unsigned int *)(reg)))=(unsigned int)(data))
#ifndef NDS32_INTR_DEF
/*
* NDS32_REG_SET_BITS(addr, mask)
* Do set bits to 1 at specified location
* Operation: *addr = (*addr | mask)
*/
#define NDS32_SET_BITS(addr, mask) outw(addr, inw(addr) | mask)
/*
* NDS32_REG_WAIT4_BIT_ON(addr, mask)
* Read the contents at addr and use mask to
* mask off unused bits then wait until all of
* the remaining bits are on
*
* Operation: while(!(*addr & mask));
*/
#define NDS32_REG_WAIT4_BIT_ON(addr, mask) while(0 == (inw(addr) & mask))
/*
* NDS32_REG_WAIT4_BIT_OFF(addr, mask)
* Read the contents at addr and use mask to
* mask off unused bits then wait until all of
* the remaining bits are off
*
* Operation: while((*addr & mask));
*/
#define NDS32_REG_WAIT4_BIT_OFF(addr, mask) while(inw(addr) & mask)
/*
* NDS32_REG_WRITE(addr, data)
* Write data to specified location at addr
*
* Operation: *addr = data
* */
#define NDS32_REG_WRITE(addr, data) outw(addr, data)
/*
* NDS32_FMEMCPY_BYTE(dst, src, size)
* Do forward (low address to high address) memory copy in byte
* */
#define NDS32_FMEMCPY_BYTE(dst, src, size) \
__asm__ __volatile__( \
"sethi $r3, hi20(%2) \n\t" \
"ori $r3, $r3, lo12(%2) \n\t" \
"sethi $r1, hi20(%0) \n\t" \
"ori $r1, $r1, lo12(%0) \n\t" \
"sethi $r2, hi20(%1) \n\t" \
"ori $r2, $r2, lo12(%1) \n\t" \
"1:\n\t" \
"lbi.bi $r0, [$r2], 1 \n\t" \
"sbi.bi $r0, [$r1], 1 \n\t" \
"addi $r3, $r3, -1 \n\t" \
"bnez $r3, 1b \n\t" \
::"i"(dst),"i"(src),"i"(size):"$r0", "$r1","$r2","$r3")
#define NDS32_FMEMCPY(dst, src, size) \
__asm__ __volatile__( \
"sethi $r3, hi20(%2) \n\t" \
"ori $r3, $r3, lo12(%2) \n\t" \
"sethi $r1, hi20(%0) \n\t" \
"ori $r1, $r1, lo12(%0) \n\t" \
"sethi $r2, hi20(%1) \n\t" \
"ori $r2, $r2, lo12(%1) \n\t" \
"1:\n\t" \
"lwi.bi $r0, [$r2], 4 \n\t" \
"swi.bi $r0, [$r1], 4 \n\t" \
"addi $r3, $r3, -4 \n\t" \
"bgtz $r3, 1b \n\t" \
::"i"(dst),"i"(src),"i"(size):"$r0", "$r1","$r2","$r3")
#endif
/************************************
* HAL Level : Memory interface *
************************************/
#define AG101P_SDRAM_INIT() \
{ \
/* SDRAM controller - set timing parameter */ \
NDS32_REG_WRITE(SDRAMC_BASE + PARM1_OFFSET, SDRAMC_PARM1_INIT);\
NDS32_REG_WRITE(SDRAMC_BASE + PARM2_OFFSET, SDRAMC_PARM2_INIT);\
/* SDRAM controller - set config register */ \
NDS32_REG_WRITE(SDRAMC_BASE + CONFIG1_OFFSET, SDRAMC_CONFIG1_INIT);\
/* refer to ATFSDMC appendix, and boot.S of bootcode */ \
NDS32_REG_WRITE(SDRAMC_BASE + CONFIG2_OFFSET, SDRAMC_CONFIG2_INIT);\
NDS32_REG_WAIT4_BIT_OFF(SDRAMC_BASE + CONFIG2_OFFSET, 0x1c);\
NDS32_REG_WRITE(SDRAMC_BASE + CONFIG2_OFFSET, 0x4); \
NDS32_REG_WAIT4_BIT_OFF(SDRAMC_BASE + CONFIG2_OFFSET, 0x1c);\
NDS32_REG_WRITE(SDRAMC_BASE + CONFIG2_OFFSET, 0x8); \
NDS32_REG_WAIT4_BIT_OFF(SDRAMC_BASE + CONFIG2_OFFSET, 0x1c);\
}
#define HAL_MEMORY_SETUP(_base_) \
do { \
/* static memory bank 0 timing parameter register */ \
NDS32_REG_WRITE(SMC_BASE + BANK0TPR_OFFSET, SMC_BANK0TPR_INIT);\
/* PMU - PLL/DLL Control Register 0 - Enable DLL */ \
NDS32_SET_BITS(PMUC_BASE + PLLDLLCR0_OFFSET, 0x00010000); \
/* Initial SDRAM controller */ \
AG101P_SDRAM_INIT(); \
/* Enable SDRAM */ \
NDS32_REG_WRITE(SDRAMC_BASE + 0x10, 0x1000 | (_base_ >> 20));\
/* RAM (base,size) : (base, 2GB)(4GB mode) / (base, 8MB)(16MB mode) */ \
NDS32_REG_WRITE(AHBC_BASE + DEVICE6_OFFSET, _base_ | AHBC_DEV6_SIZE_INIT);\
} while(0)
#define HAL_MEMORY_REMAP() \
do { \
/* Remapping */ \
/* Bank Enable, BASE = 0x100 for haddr[31:20] of the AHB address bus. */\
/* External Bank Configuration Registers */ \
NDS32_REG_WRITE(SDRAMC_BASE + 0x14, 0x0); \
NDS32_REG_WRITE(SDRAMC_BASE + 0x18, 0x0); \
NDS32_REG_WRITE(SDRAMC_BASE + 0x1c, 0x0); \
/* Bank Enable, BASE = 0x0 for haddr[31:20] of the AHB address bus. */ \
NDS32_REG_WRITE(SDRAMC_BASE + 0x10, 0x1000); \
/* When writing a 1 to this bit, the base/size configuration\
* of AHB slaves 4 (ROM) and 6 (SDRAM/DDR) will be interchanged. */ \
NDS32_SET_BITS(AHBC_BASE + INTC_OFFSET, 0x1); \
} while(0)
#define HAL_MEMORY_REMAP_ADJUST() \
do { \
NDS32_REG_WRITE(AHBC_BASE + DEVICE6_OFFSET, 0x000 | AHBC_DEV6_SIZE_REMAP);\
} while(0)
/************************************
* HAL Level : Interrupt *
************************************/
#define HW_ISR(hw) HW##hw##_ISR
#define NEW_HW_ISR(hw) NEW##_HW##hw##_ISR
#define SET_HWISR(hw) HW_ISR(hw)
#define NEW_SET_HWISR(hw) NEW_HW_ISR(hw)
#if !defined(CFG_16MB) && !defined(CFG_EVIC)
/* ISR function name for interrupt controller platform */
#define FIQ_ISR SET_HWISR(HW0_FIQ)
#define IRQ_ISR SET_HWISR(HW1_IRQ)
#define NEW_IRQ_ISR NEW_SET_HWISR(NEW_HW1_IRQ)
#define SW0_ISR SET_HWISR(HW6_SW0)
#endif
/* ISR function name for 32IVIC/EVIC platform */
#define SWI_ISR SET_HWISR(IRQ_SWI)
#define GPIO_ISR SET_HWISR(IRQ_GPIO)
#define TIMER_ISR SET_HWISR(IRQ_TIMER1)
#ifdef CFG_16MB
/* AG101P 16MB platform without interrupt controller */
#define HAL_INTC_HWIRQ_ROUTE(_vector_, _hw_)
#define HAL_INTC_IRQ_CONFIGURE(_irqs_, _edge_, _falling_)
#define HAL_INTC_IRQ_MASK(_irqs_)
#define HAL_INTC_IRQ_UNMASK(_irqs_)
#define HAL_INTC_IRQ_CLEAR(_irqs_)
#define HAL_INTC_FIQ_CONFIGURE(_irqs_, _edge_, _falling_)
#define HAL_INTC_FIQ_MASK(_irqs_)
#define HAL_INTC_FIQ_UNMASK(_irqs_)
#define HAL_INTC_FIQ_CLEAR(_irqs_)
#else
/* HAL for interrupt controller */
#define HAL_INTC_HWIRQ_ROUTE(_vector_, _hw_)
#define HAL_INTC_IRQ_CONFIGURE(_irqs_, _edge_, _falling_) \
do { \
if (_edge_) { \
outw(INTC_BASE + IRQTMR_OFFSET, \
inw(INTC_BASE + IRQTMR_OFFSET) | (_irqs_)); \
} else { \
outw(INTC_BASE + IRQTMR_OFFSET, \
inw(INTC_BASE + IRQTMR_OFFSET) & ~(_irqs_));\
} \
if (_falling_) { \
outw(INTC_BASE + IRQTLR_OFFSET, \
inw(INTC_BASE + IRQTLR_OFFSET) | (_irqs_)); \
} else { \
outw(INTC_BASE + IRQTLR_OFFSET, \
inw(INTC_BASE + IRQTLR_OFFSET) & ~(_irqs_));\
} \
} while(0)
#define HAL_INTC_IRQ_MASK(_irqs_) \
outw(INTC_BASE + IRQER_OFFSET, \
inw(INTC_BASE + IRQER_OFFSET) & ~(_irqs_))
#define HAL_INTC_IRQ_UNMASK(_irqs_) \
outw(INTC_BASE + IRQER_OFFSET, \
inw(INTC_BASE + IRQER_OFFSET) | (_irqs_))
#define HAL_INTC_IRQ_CLEAR(_irqs_) \
outw(INTC_BASE + IRQICR_OFFSET, (_irqs_))
#define HAL_INTC_FIQ_CONFIGURE(_irqs_, _edge_, _falling_) \
do { \
if (_edge_) { \
outw(INTC_BASE + FIQTMR_OFFSET, \
inw(INTC_BASE + FIQTMR_OFFSET) | (_irqs_)); \
} else { \
outw(INTC_BASE + FIQTMR_OFFSET, \
inw(INTC_BASE + FIQTMR_OFFSET) & ~(_irqs_));\
} \
if (_falling_) { \
outw(INTC_BASE + FIQTLR_OFFSET, \
inw(INTC_BASE + FIQTLR_OFFSET) | (_irqs_)); \
} else { \
outw(INTC_BASE + FIQTLR_OFFSET, \
inw(INTC_BASE + FIQTLR_OFFSET) & ~(_irqs_));\
} \
} while(0)
#define HAL_INTC_FIQ_MASK(_irqs_) \
outw(INTC_BASE + FIQER_OFFSET, \
inw(INTC_BASE + FIQER_OFFSET) & ~(_irqs_))
#define HAL_INTC_FIQ_UNMASK(_irqs_) \
outw(INTC_BASE + FIQER_OFFSET, \
inw(INTC_BASE + FIQER_OFFSET) | (_irqs_))
#define HAL_INTC_FIQ_CLEAR(_irqs_) \
outw(INTC_BASE + FIQICR_OFFSET, (_irqs_))
#endif
/************************************
* HAL Level : Timer *
************************************/
#define HAL_TIMER_INITIALIZE() \
do { \
outw(TM_CR, 0); \
outw(TM_MTCH1(0), 0); \
outw(TM_MTCH1(1), 0); \
outw(TM_MTCH1(2), 0); \
outw(TM_MSK, 0); \
outw(TM_STA, 0xFFFFFFFF); \
} while(0)
#define HAL_TIMER_START(_tmr_) \
outw(TM_CR, inw(TM_CR) | (0x1 << (3 * (_tmr_))))
#define HAL_TIMER_STOP(_tmr_) \
outw(TM_CR, inw(TM_CR) & ~(0x1 << (3 * (_tmr_))))
#define HAL_TIMER_READ(_tmr_, _pvalue_) \
*(volatile unsigned int *)_pvalue_ = \
inw(TM_LOAD(_tmr_)) - inw(TM_CNTR(_tmr_))
#define HAL_TIMER_SET_PERIOD(_tmr_, _period_) \
do { \
outw(TM_LOAD(_tmr_), _period_); \
outw(TM_CNTR(_tmr_), _period_); \
} while(0)
#define HAL_TIMER_IRQ_ENABLE(_tmr_, _ie_) \
do { \
if(_ie_) \
outw(TM_MSK, inw(TM_MSK) & ~(0x1 << (3 * (_tmr_))));\
else \
outw(TM_MSK, inw(TM_MSK) | (0x1 << (3 * (_tmr_)))); \
} while(0)
#define HAL_TIMER_IRQ_STATUS(_tmr_, _pvalue_) \
*(volatile unsigned int *)_pvalue_ = \
(inw(TM_STA) & (0x7 << (3 * (_tmr_))))
#define HAL_TIMER_IRQ_CLR(_tmr_) \
outw(TM_STA, (0x7 << (3 * (_tmr_))))
/************************************
* HAL Level : GPIO *
************************************/
#define HAL_GPIO_INITIALIZE(_pin_) \
do { \
outw(GPIO_BASE + GPIO_DIR_OFFSET, \
inw(GPIO_BASE + GPIO_DIR_OFFSET) & ~_pin_); \
outw(GPIO_BASE + GPIO_IR_OFFSET, \
inw(GPIO_BASE + GPIO_IR_OFFSET) | _pin_); \
outw(GPIO_BASE + GPIO_DCLEAR_OFFSET, -1); \
outw(GPIO_BASE + GPIO_BPS_OFFSET, 0x0000FFFF); \
outw(GPIO_BASE + GPIO_BE_OFFSET, _pin_); \
outw(GPIO_BASE + GPIO_IC_OFFSET, -1); \
outw(GPIO_BASE + GPIO_IE_OFFSET, _pin_); \
} while(0)
#define HAL_GPIO_READ() inw(GPIO_BASE + GPIO_DIN_OFFSET)
#define HAL_GPIO_IRQ_CLR(_pin_) outw(GPIO_BASE + GPIO_IC_OFFSET, _pin_)
#ifdef __ASSEMBLY__
/************************************
* HAL : AG101P defined vectors *
************************************/
.macro hal_hw_vectors
#if defined(CFG_16MB) || defined(CFG_EVIC)
vector Interrupt_UNDEF // (9) Interrupt HW0
vector Interrupt_UNDEF // (10) Interrupt HW1
vector Interrupt_UNDEF // (11) Interrupt HW2
vector Interrupt_UNDEF // (12) Interrupt HW3
vector Interrupt_UNDEF // (13) Interrupt HW4
vector Interrupt_UNDEF // (14) Interrupt HW5
vector Interrupt_UNDEF // (15) Interrupt HW6
#else
vector Interrupt_HW0 // (9) Interrupt HW0 (for IVB.IVIC_VER = 0, FIR)
vector Interrupt_HW1 // (10) Interrupt HW1 (for IVB.IVIC_VER = 0, IRQ)
vector Interrupt_UNDEF // (11) Interrupt HW2
vector Interrupt_UNDEF // (12) Interrupt HW3
vector Interrupt_UNDEF // (13) Interrupt HW4
vector Interrupt_UNDEF // (14) Interrupt HW5
vector Interrupt_HW6 // (15) Interrupt HW6 (for IVB.IVIC_VER = 0, SW0)
#endif
vector Interrupt_UNDEF // (16) Interrupt HW7
vector Interrupt_UNDEF // (17) Interrupt HW8
vector Interrupt_HW9 // (18) Interrupt HW9 (32IVIC, SWI)
vector Interrupt_UNDEF // (19) Interrupt HW10
vector Interrupt_UNDEF // (20) Interrupt HW11
vector Interrupt_UNDEF // (21) Interrupt HW12
vector Interrupt_HW13 // (22) Interrupt HW13 (32IVIC, GPIO)
vector Interrupt_UNDEF // (23) Interrupt HW14
vector Interrupt_UNDEF // (24) Interrupt HW15
vector Interrupt_UNDEF // (25) Interrupt HW16
vector Interrupt_UNDEF // (26) Interrupt HW17
vector Interrupt_UNDEF // (27) Interrupt HW18
vector Interrupt_HW19 // (28) Interrupt HW19 (32IVIC, TIMER)
vector Interrupt_UNDEF // (29) Interrupt HW20
vector Interrupt_UNDEF // (30) Interrupt HW21
vector Interrupt_UNDEF // (31) Interrupt HW22
vector Interrupt_UNDEF // (32) Interrupt HW23
vector Interrupt_UNDEF // (33) Interrupt HW24
vector Interrupt_UNDEF // (34) Interrupt HW25
vector Interrupt_UNDEF // (35) Interrupt HW26
vector Interrupt_UNDEF // (36) Interrupt HW27
vector Interrupt_UNDEF // (37) Interrupt HW28
vector Interrupt_UNDEF // (38) Interrupt HW29
vector Interrupt_UNDEF // (39) Interrupt HW30
vector Interrupt_UNDEF // (40) Interrupt HW31
.endm
.macro hal_hw_ISR
#if !defined(CFG_16MB) && !defined(CFG_EVIC)
Os_Trap_Interrupt_HW HW0_FIQ
Os_Trap_Interrupt_HW HW1_IRQ
Os_Trap_Interrupt_HW HW6_SW0
#endif
Os_Trap_Interrupt_HW IRQ_SWI
Os_Trap_Interrupt_HW IRQ_GPIO
Os_Trap_Interrupt_HW IRQ_TIMER1
.endm
.macro hal_hw_new_vectors
#if defined(CFG_16MB) || defined(CFG_EVIC)
vector Interrupt_UNDEF // (9) Interrupt HW0
vector Interrupt_UNDEF // (10) Interrupt HW1
vector Interrupt_UNDEF // (11) Interrupt HW2
vector Interrupt_UNDEF // (12) Interrupt HW3
vector Interrupt_UNDEF // (13) Interrupt HW4
vector Interrupt_UNDEF // (14) Interrupt HW5
vector Interrupt_UNDEF // (15) Interrupt HW6
#else
vector Interrupt_UNDEF // (9) Interrupt HW0 (for IVB.IVIC_VER = 0, FIR)
vector Interrupt_NEW_HW1 // (10) Interrupt HW1 (for IVB.IVIC_VER = 0, IRQ)
vector Interrupt_UNDEF // (11) Interrupt HW2
vector Interrupt_UNDEF // (12) Interrupt HW3
vector Interrupt_UNDEF // (13) Interrupt HW4
vector Interrupt_UNDEF // (14) Interrupt HW5
vector Interrupt_UNDEF // (15) Interrupt HW6 (for IVB.IVIC_VER = 0, SW0)
#endif
vector Interrupt_UNDEF // (16) Interrupt HW7
vector Interrupt_UNDEF // (17) Interrupt HW8
vector Interrupt_UNDEF // (18) Interrupt HW9 (32IVIC, SWI)
vector Interrupt_UNDEF // (19) Interrupt HW10
vector Interrupt_UNDEF // (20) Interrupt HW11
vector Interrupt_UNDEF // (21) Interrupt HW12
vector Interrupt_UNDEF // (22) Interrupt HW13 (32IVIC, GPIO)
vector Interrupt_UNDEF // (23) Interrupt HW14
vector Interrupt_UNDEF // (24) Interrupt HW15
vector Interrupt_UNDEF // (25) Interrupt HW16
vector Interrupt_UNDEF // (26) Interrupt HW17
vector Interrupt_UNDEF // (27) Interrupt HW18
vector Interrupt_UNDEF // (28) Interrupt HW19 (32IVIC, TIMER)
vector Interrupt_UNDEF // (29) Interrupt HW20
vector Interrupt_UNDEF // (30) Interrupt HW21
vector Interrupt_UNDEF // (31) Interrupt HW22
vector Interrupt_UNDEF // (32) Interrupt HW23
vector Interrupt_UNDEF // (33) Interrupt HW24
vector Interrupt_UNDEF // (34) Interrupt HW25
vector Interrupt_UNDEF // (35) Interrupt HW26
vector Interrupt_UNDEF // (36) Interrupt HW27
vector Interrupt_UNDEF // (37) Interrupt HW28
vector Interrupt_UNDEF // (38) Interrupt HW29
vector Interrupt_UNDEF // (39) Interrupt HW30
vector Interrupt_UNDEF // (40) Interrupt HW31
.endm
.macro hal_hw_new_ISR
Os_Trap_Interrupt_NEW_HW NEW_HW1_IRQ
.endm
.macro hal_set_led, val
li $r0, \val
li $r1, LED_BASE
swi $r0, [$r1]
.endm
#endif /* __ASSEMBLY__ */
#endif /* AG101P_REGS */
demo-int-new-ivbase/src/ag102.h 0000644 0 0 63474 12415051334 14232 0 ustar 00nobody nobody #ifndef AG102_REGS
#define AG102_REGS
/* Check to see if this file has been included already. */
#ifndef __ASSEMBLY__
#include
#endif
/* System Clock */
#define MHz 1000000
#define CPUFREQ (495 * MHz)
#define HCLKFREQ (123 * MHz)
#define PCLKFREQ (61 * MHz)
#define UCLKFREQ (33 * MHz)
/* Different memory size defines used by SDRAM initialization */
#define SDRAM_256MB 0x0100
#define SDRAM_128MB 0x00C0
#define SDRAM_64MB 0x0040
#define SDRAM_32MB 0x0004
#define SDRAM_16MB 0x0000
#define ORIG_RAM_BASE 0x80000000
#define REMAP_ROM_BASE ORIG_RAM_BASE
/************************************
* TARGET TIMER CONSTANTS *
************************************/
#define DDR2C_BASE 0x90500000 /* Define base for all ddr2 controller registers */
#define DDR2C_CCR_OFFSET 0x00 /* Controller Configuration Register */
#define DDR2C_DCR_OFFSET 0x04 /* DRAM Configuration Register */
#define DDR2C_IOCR_OFFSET 0x08 /* I/O Configuration Register */
#define DDR2C_CSR_OFFSET 0x0C /* Controller Status Register */
#define DDR2C_DRR_OFFSET 0x10 /* DRAM Refresh Register */
#define DDR2C_TPR_OFFSET(N) (0x14 + 4 * (N)) /* SDRAM Timing Parameters Registers 0-2 */
#define DDR2C_GDLLCR_OFFSET 0x20 /* Global DLL Control Register */
#define DDR2C_DLLCR_OFFSET(N) (0x24 + 4 * (N)) /* DLL Control Registers 0-9 */
#define DDR2C_RSLR_OFFSET(N) (0x4C + 4 * (N)) /* Rank System Latency Registers 0-3 */
#define DDR2C_RDGR_OFFSET(N) (0x5C + 4 * (N)) /* Rank DQS Gating Registers 0-3 */
#define DDR2C_DQTR_OFFSET(N) (0x6C + 4 * (N)) /* DQ Timing Registers 0-8 */
#define DDR2C_DQSTR_OFFSET 0x90 /* DQS Timing Register */
#define DDR2C_DQSBTR_OFFSET 0x94 /* DQS_b Timing Register */
#define DDR2C_ODTCR_OFFSET 0x98 /* ODT Configuration Register */
#define DDR2C_DTR_OFFSET(N) (0x9C + 4 * (N)) /* Data Training Registers 0-1 */
#define DDR2C_DTAR_OFFSET 0xA4 /* Data Training Address Register */
#define DDR2C_MR_OFFSET 0x1F0 /* Mode Register */
/************************************
* TARGET TIMER CONSTANTS *
************************************/
#define TIMER_BASE 0x94900000 /* Define base for all timer registers */
#define TIMER_CNT_OFFSET(N) (0x00 + 0x10 * (N)) /* Offset for timer N counter register */
#define TIMER_LOAD_OFFSET(N) (0x04 + 0x10 * (N)) /* Offset for timer N load register */
#define TIMER_MATCH1_OFFSET(N) (0x08 + 0x10 * (N)) /* Offset for timer N match1 register */
#define TIMER_MATCH2_OFFSET(N) (0x0C + 0x10 * (N)) /* Offset for timer N match2 register */
#define TIMER_CNTRL_OFFSET 0x30 /* Offset for timer control register */
#define TIMER_INTS_OFFSET 0x34 /* Offset for timer interrupt status register */
#define TIMER_INTM_OFFSET 0x38 /* Offset for timer interrupt mask register */
/* Timer 1 ~ 3, ATC010 */
#define TM_CNTR(N) (TIMER_BASE + TIMER_CNT_OFFSET(N))
#define TM_LOAD(N) (TIMER_BASE + TIMER_LOAD_OFFSET(N))
#define TM_MTCH1(N) (TIMER_BASE + TIMER_MATCH1_OFFSET(N))
#define TM_MTCH2(N) (TIMER_BASE + TIMER_MATCH2_OFFSET(N))
#define TM_CR (TIMER_BASE + TIMER_CNTRL_OFFSET)
#define TM_STA (TIMER_BASE + TIMER_INTS_OFFSET)
#define TM_MSK (TIMER_BASE + TIMER_INTM_OFFSET)
/************************************
* TARGET INTERRUPT CONSTANTS *
************************************/
#define INTC_BASE 0x90F00000 /* Interrupt Controller base address */
#define IRQREV_OFFSET 0x0 /* INTC revision register */
#define IRQOWNER_OFFSET 0x4 /* CPU owner DC regsiter */
#define IRQCPUID0_OFFSET 0x8 /* CPU ID configuration register for interrupt input 0-15 */
#define IRQCPUID1_OFFSET 0xc /* CPU ID configuration register for interrupt intpu 16-31 */
#define IRQTMR_OFFSET 0x20 /* Interrupt trigger mode register */
#define IRQTLR_OFFSET 0x24 /* Interrupt trigger level register */
#define FIQTMR_OFFSET IRQTMR_OFFSET
#define FIQTLR_OFFSET IRQTLR_OFFSET
#define IRQSRC_OFFSET 0x28 /* Interrupt source register */
#define IRQIPI_TRIG_OFFSET 0x40 /* IPI trigger register */
#define IRQIPI_STAT_OFFSET 0x44 /* IPI status / clear register */
#define IRQIPI_PRIO_OFFSET 0x48 /* IPI priority level register */
#define IRQIPIGLB_STAT_OFFSET 0x4c /* IPI global status / clear register */
#define IRQIPIGLB_PRIO_OFFSET 0x50 /* IPI global priority register */
#define IRQER_OFFSET 0x80 /* Interrupt enable register */
#define IRQICR_OFFSET 0x84 /* Interrupt status / clear register */
#define FIQER_OFFSET IRQER_OFFSET
#define FIQICR_OFFSET IRQICR_OFFSET
#define IRQICR_IVIC_OFFSET(N) (0x88 + 4*(N)) /* IVIC HW0 ~ HW5 interrupt status / clear register */
#define IRQPRI_OFFSET(N) (0xa0 + 4 *(N))/* Interrupt priority level configuration for interrupt input 0-7 */
#define INT_ER_INIT 0x00000000 /* values used to disable all interrupts */
#define INT_CLEAR_VALUE 0xFFFFFFFF /* values used to clear all pending interrupts */
/************************************
* TARGET DECODER CONSTANTS *
************************************/
#define AHBC_BASE 0x90C00000 /* AHB Controller base address */
#define DEVICE4_OFFSET 0x10 /* Device 4 Control Register offset */
#define DEVICE6_OFFSET 0x18 /* Device 6 Control Register offset */
#define INTC_OFFSET 0x88 /* Interrupt Control Register offset */
#define AHBC_DEV6_INIT 0x10080000 /* AHBC Device 6 init value */
#define AHBC_REMAP_BIT 0x00000001 /* AHBC remap bit for Interrupt Control Register */
/************************************
* PCU - AG102 Core APB *
************************************/
#define PCU_BASE 0x94800000 /* Device base address */
#define PCU_RR_OFFSET 0x00 /* PCU revision register */
#define PCU_SPIR_OFFSET 0x04 /* Scratch pad info register */
#define PCU_SOCID_OFFSET 0x10 /* SoC ID */
#define PCU_AHBCFG_OFFSET 0x14 /* SoC AHB configuration register */
#define PCU_APBCFG_OFFSET 0x18 /* SoC APB configuration register */
#define PCU_DCSRC0_OFFSET 0x20 /* Driving capability and slew rate control register 0 */
#define PCU_DCSRC1_OFFSET 0x24 /* Driving capability and slew rate control register 1 */
#define PCU_DCSRC2_OFFSET 0x28 /* Driving capability and slew rate control register 2 */
#define PCU_MFPS0_OFFSET 0x30 /* Multi-Function port setting register 0 */
#define PCU_MFPS1_OFFSET 0x34 /* Multi-Function port setting register 1 */
#define PCU_DMASEL_OFFSET 0x38 /* DMA engine selection */
#define PCU_OSCC_OFFSET 0x40 /* OSC control register */
#define PCU_PWMCD_OFFSET 0x44 /* PMW clock divider */
#define PCU_SOC_MISC_OFFSET 0x48 /* SoC misc */
#define PCU_BSMC_OFFSET 0x80 /* BSM control register */
#define PCU_BSMS_OFFSET 0x84 /* BSM status register */
#define PCU_WESENS_OFFSET 0x88 /* Wakeup event sensitivity register */
#define PCU_WESTAT_OFFSET 0x8c /* Wakeup event status register */
#define PCU_RT_OFFSET 0x90 /* Reset timing register */
#define PCU_ISR_OFFSET 0x94 /* PCU interrupt status register */
#define PCU_PMSP_MEM0_OFFSET(N) (0x400 + 4 * (N)) /* Power Manager Scratch Pad Memory 0 */
/* PCSn registers (n = 1 ~ 9) */
#define PCU_PCSC_OFFSET(N) (0xa0 + 0x20 * ((N) - 1)) /* PCSn configuration register (clock scaling slot) */
#define PCU_PCSP_OFFSET(N) (0xa4 + 0x20 * ((N) - 1)) /* PCSn parameter register (clock scaling slot) */
#define PCU_PCSSTAT1_OFFSET(N) (0xa8 + 0x20 * ((N) - 1)) /* PCSn status register 1 (clock scaling slot) */
#define PCU_PCSSTAT2_OFFSET(N) (0xac + 0x20 * ((N) - 1)) /* PCSn status register 2 (clock scaling slot) */
#define PCU_PSC1PDD_OFFSET(N) (0xb0 + 0x20 * ((N) - 1)) /* PCSn PDD register (clock scaling slot) */
/************************************
* TARGET GPIO CONSTANTS *
************************************/
#define GPIO_BASE 0x94C00000 /* GPIO base address */
#define GPIO_DOUT_OFFSET 0x0
#define GPIO_DIN_OFFSET 0x4
#define GPIO_DIR_OFFSET 0x8
#define GPIO_DSET_OFFSET 0x10
#define GPIO_DCLEAR_OFFSET 0x14
#define GPIO_PE_OFFSET 0x18
#define GPIO_PT_OFFSET 0x1C
#define GPIO_IE_OFFSET 0x20
#define GPIO_IS_OFFSET 0x24
#define GPIO_IT_OFFSET 0x34
#define GPIO_IC_OFFSET 0x30
#define GPIO_IB_OFFSET 0x38
#define GPIO_IR_OFFSET 0x3c
#define GPIO_BE_OFFSET 0x40 /* BounceEnable */
#define GPIO_BPS_OFFSET 0x44 /* BouncePreScale */
#define GPIO_USED_GCOV 0x02 /* Which GPIO to do GCOV */
#define GPIO_USED_MASK 0x0A /* Which GPIOs to use */
/************************************
* TARGET UART CONSTANTS *
************************************/
#define UART_BASE 0x94200000 //0x99600000
#define UART_RBR_OFFSET 0x00 /* Receiver Buffer Register for Read */
#define UART_THR_OFFSET 0x00 /* Transmitter Holding Register for Write */
#define UART_IER_OFFSET 0x04 /* Interrupt Enable Register */
/* Baud-Rate Divisor Latch (DL, Offset: 0x00, 0x04 when DLAB = 1) */
#define UART_DLL_OFFSET 0x00
#define UART_DLM_OFFSET 0x04
#define UART_IIR_OFFSET 0x08 /* Interrupt Identification Register */
#define UART_FCR_OFFSET 0x08 /* FIFO Control Register */
/* Prescaler Register (PSR, Offset: 0x08 when DLAB =1) */
#define UART_LCR_OFFSET 0x0C /* Line Control Register */
#define UART_MCR_OFFSET 0x10 /* Modem Control Register */
#define UART_LSR_OFFSET 0x14 /* Line Status Register for Read */
#define UART_TST_OFFSET 0x14 /* Testing Register for Write */
#define UART_MSR_OFFSET 0x18 /* Modem Status Register */
#define UART_SPR_OFFSET 0x1C /* Scratch Pad Register */
#define UART_MDR_OFFSET 0x20 /* Mode Definition Register */
#define UART_ACR_OFFSET 0x24 /* Auxiliary Control Register */
#define UART_TXLENL_OFFSET 0x28 /* Transmit Frame-Length Register (Low) */
#define UART_TXLENH_OFFSET 0x2C /* Transmit Frame-Length Register (High)*/
#define UART_MRXLENL_OFFSET 0x30 /* Maximum Receiver Frame-Length (Low) */
#define UART_MRXLENH_OFFSET 0x34 /* Maximum Receiver Frame-Length (High)*/
#define UART_PLR_OFFSET 0x38 /* Preamble Length Register */
#define UART_FMIIR_PIO_OFFSET 0x3C /* Interrupt Identification Register in FIR Mode (PIO mode) */
#define UART_FMIIR_DMA_OFFSET 0x3C /* Interrupt Identification Register in FIR Mode (DMA mode) */
#define UART_FMIIER_PIO_OFFSET 0x40 /* Interrupt Identification Enable Register in FIR Mode (PIO mode) */
#define UART_FMIIER_DMA_OFFSET 0x40 /* Interrupt Identification Enable Register in FIR Mode (DMA mode) */
#define UART_STFF_STS_OFFSET 0x44 /* Status FIFO Line Status Register */
#define UART_STFF_RXLENL_OFFSET 0x48 /* Status FIFO Received Frame-Length Register Low */
#define UART_STFF_RXLENH_OFFSET 0x4C /* Status FIFO Received Frame-Length Register High */
#define UART_FMLSR_OFFSET 0x50 /* Link Status Register in FIR Mode */
#define UART_FMLSIER_OFFSET 0x54 /* Link Status Interrupt Enable Register in FIR Mode */
#define UART_RSR_OFFSET 0x58 /* Resume Register */
#define UART_RXFF_CNTR_OFFSET 0x5C /* RX FIFO Count Register */
#define UART_LSTFMLENL_OFFSET 0x60 /* Last Frame Length Register Low */
#define UART_LSTFMLENH_OFFSET 0x64 /* Last Frame Length Register High */
#define UART_FEATURE_OFFSET 0x68 /* Feature Register */
#define UART_REVD1_OFFSET 0x6C /* Revision Register Digit 1 */
#define UART_REVD2_OFFSET 0x70 /* Revision Register Digit 2 */
#define UART_REVD3_OFFSET 0x74 /* Revision Register Digit 3 */
/************************************
* IRQ number *
************************************/
#define HW0_FIQ 0
#define HW1_IRQ 1
#define HW6_SW0 6
/* Interrupt controller IRQ mapping */
#define IRQ_CFC_CD 0
#define IRQ_CFC_DMA 1
#define IRQ_SSP1 2
#define IRQ_I2C 3
#define IRQ_SDC 5
#define IRQ_SSP2 6
#define IRQ_STUART 7
#define IRQ_PMU 8
#define IRQ_SWI 9
#define IRQ_FTUART 10
#define IRQ_BTUART 11
#define IRQ_EXTINT5 12
#define IRQ_GPIO 13
#define IRQ_TIMER2 14
#define IRQ_TIMER3 15
#define IRQ_WDT 16
#define IRQ_RTCALARM 17
#define IRQ_RTCSECOND 18
#define IRQ_TIMER1 19
#define IRQ_CPE_AHB_DMA 21
#define IRQ_CPE_APB_DMA 24
#define IRQ_MAC 25
#define IRQ_USBDEV 26 // USB device
#define IRQ_EXTINT4 27
#define IRQ_EXTINT0 28
#define IRQ_EXTINT1 29
#define IRQ_EXTINT2 30
#define IRQ_EXTINT3 31
/* interrupt sources */
#define IC_SWI (1 << IRQ_SWI)
#define IC_GPIO (1 << IRQ_GPIO)
#define IC_TIMER1 (1 << IRQ_TIMER1)
#define IC_TIMER2 (1 << IRQ_TIMER2)
#define IC_TIMER3 (1 << IRQ_TIMER3)
/* Low-level port I/O */
#define inw(reg) (*((volatile unsigned int *) (reg)))
#define outw(reg, data) ((*((volatile unsigned int *)(reg)))=(unsigned int)(data))
#ifndef NDS32_INTR_DEF
/*
* NDS32_REG_SET_BITS(addr, mask)
* Do set bits to 1 at specified location
* Operation: *addr = (*addr | mask)
*/
#define NDS32_SET_BITS(addr, mask) outw(addr, inw(addr) | mask)
/*
* NDS32_REG_WAIT4_BIT_ON(addr, mask)
* Read the contents at addr and use mask to
* mask off unused bits then wait until all of
* the remaining bits are on
*
* Operation: while(!(*addr & mask));
*/
#define NDS32_REG_WAIT4_BIT_ON(addr, mask) while(0 == (inw(addr) & mask))
/*
* NDS32_REG_WAIT4_BIT_OFF(addr, mask)
* Read the contents at addr and use mask to
* mask off unused bits then wait until all of
* the remaining bits are off
*
* Operation: while((*addr & mask));
*/
#define NDS32_REG_WAIT4_BIT_OFF(addr, mask) while(inw(addr) & mask)
/*
* NDS32_REG_WRITE(addr, data)
* Write data to specified location at addr
*
* Operation: *addr = data
* */
#define NDS32_REG_WRITE(addr, data) outw(addr, data)
#define NDS32_REG_READ(addr) inw(addr)
/*
* NDS32_FMEMCPY_BYTE(dst, src, size)
* Do forward (low address to high address) memory copy in byte
* */
#define NDS32_FMEMCPY_BYTE(dst, src, size) \
__asm__ __volatile__( \
"sethi $r3, hi20(%2) \n\t" \
"ori $r3, $r3, lo12(%2) \n\t" \
"sethi $r1, hi20(%0) \n\t" \
"ori $r1, $r1, lo12(%0) \n\t" \
"sethi $r2, hi20(%1) \n\t" \
"ori $r2, $r2, lo12(%1) \n\t" \
"1:\n\t" \
"lbi.bi $r0, [$r2], 1 \n\t" \
"sbi.bi $r0, [$r1], 1 \n\t" \
"addi $r3, $r3, -1 \n\t" \
"bnez $r3, 1b \n\t" \
::"i"(dst),"i"(src),"i"(size):"$r0", "$r1","$r2","$r3")
#define NDS32_FMEMCPY(dst, src, size) \
__asm__ __volatile__( \
"sethi $r3, hi20(%2) \n\t" \
"ori $r3, $r3, lo12(%2) \n\t" \
"sethi $r1, hi20(%0) \n\t" \
"ori $r1, $r1, lo12(%0) \n\t" \
"sethi $r2, hi20(%1) \n\t" \
"ori $r2, $r2, lo12(%1) \n\t" \
"1:\n\t" \
"lwi.bi $r0, [$r2], 4 \n\t" \
"swi.bi $r0, [$r1], 4 \n\t" \
"addi $r3, $r3, -4 \n\t" \
"bgtz $r3, 1b \n\t" \
::"i"(dst),"i"(src),"i"(size):"$r0", "$r1","$r2","$r3")
#endif
/************************************
* HAL Level : Memory interface *
************************************/
#define AG102_DDR_INIT() \
do { \
/* SDRAM configure */ \
NDS32_REG_WRITE(DDR2C_BASE + DDR2C_DCR_OFFSET, 0x000025cc); \
/* Data training addr */ \
NDS32_REG_WRITE(DDR2C_BASE + DDR2C_DTAR_OFFSET, 0x00100000);\
/* Set refresh / mode / IOCR */ \
NDS32_REG_WRITE(DDR2C_BASE + DDR2C_DRR_OFFSET, 0x00034812); \
NDS32_REG_WRITE(DDR2C_BASE + DDR2C_MR_OFFSET, 0x00000852); \
NDS32_REG_WRITE(DDR2C_BASE + DDR2C_IOCR_OFFSET, 0x0000000f);\
/* Enable host ports and trigger initialization */ \
NDS32_REG_WRITE(DDR2C_BASE + DDR2C_CCR_OFFSET, 0x80020000); \
/* Wait for ddr init state to be set */ \
__nds32__isb(); \
/* Wait until the config initialization is finish */ \
while(NDS32_REG_READ(DDR2C_BASE + DDR2C_CSR_OFFSET) >> 23); \
/* Enable host ports and trigger the data training */ \
NDS32_REG_WRITE(DDR2C_BASE + DDR2C_CCR_OFFSET, 0x40020004); \
/* Wait for ddr init state to be set */ \
__nds32__isb(); \
/* Wait until the ddr data trainning is complete */ \
while(NDS32_REG_READ(DDR2C_BASE + DDR2C_CSR_OFFSET) >> 23); \
register unsigned int v; \
v = NDS32_REG_READ(DDR2C_BASE + DDR2C_CSR_OFFSET); \
NDS32_REG_WRITE(DDR2C_BASE + DDR2C_CSR_OFFSET, 0x00ffffff); \
if(!(v >> 20)) break; \
} while(1)
#define HAL_MEMORY_SETUP(_base_) \
do { \
/* Initial DDR controller */ \
AG102_DDR_INIT(); \
/* The RAM is mapped to ORIG_RAM_BASE, for use. */ \
/* ROM (base,size)=(0M,256M), RAM (base,size)=(2G,256M) */ \
NDS32_REG_WRITE(AHBC_BASE + DEVICE4_OFFSET, 0x00000000 | 0x80000); \
NDS32_REG_WRITE(AHBC_BASE + DEVICE6_OFFSET, ORIG_RAM_BASE | 0x80000);\
} while(0)
#define HAL_MEMORY_REMAP() NDS32_SET_BITS(AHBC_BASE + INTC_OFFSET, 0x1)
#define HAL_MEMORY_REMAP_ADJUST()
/************************************
* HAL Level : Interrupt *
************************************/
#define HW_ISR(hw) HW##hw##_ISR
#define SET_HWISR(hw) HW_ISR(hw)
/* ISR function name for interrupt controller platform */
#define FIQ_ISR SET_HWISR(HW0_FIQ)
#define IRQ_ISR SET_HWISR(HW1_IRQ)
#define SW0_ISR SET_HWISR(HW6_SW0)
/* HAL for interrupt controller */
#define HAL_INTC_HWIRQ_ROUTE(_vector_, _hw_) \
do { \
int n = _vector_ / 8, bits_shift = (_vector_ & 0x7 ) << 2; \
unsigned int val; \
\
val = inw(INTC_BASE + IRQPRI_OFFSET(n)) & ~(0xf << bits_shift);\
val |= ((_hw_ & 0xf) << bits_shift); \
outw(INTC_BASE + IRQPRI_OFFSET(n), val); \
} while(0)
#define HAL_INTC_IRQ_CONFIGURE(_irqs_, _edge_, _falling_) \
do { \
if (_edge_) { \
outw(INTC_BASE + IRQTMR_OFFSET, \
inw(INTC_BASE + IRQTMR_OFFSET) | (_irqs_)); \
} else { \
outw(INTC_BASE + IRQTMR_OFFSET, \
inw(INTC_BASE + IRQTMR_OFFSET) & ~(_irqs_));\
} \
if (_falling_) { \
outw(INTC_BASE + IRQTLR_OFFSET, \
inw(INTC_BASE + IRQTLR_OFFSET) | (_irqs_)); \
} else { \
outw(INTC_BASE + IRQTLR_OFFSET, \
inw(INTC_BASE + IRQTLR_OFFSET) & ~(_irqs_));\
} \
} while(0)
#define HAL_INTC_IRQ_MASK(_irqs_) \
outw(INTC_BASE + IRQER_OFFSET, \
inw(INTC_BASE + IRQER_OFFSET) & ~(_irqs_))
#define HAL_INTC_IRQ_UNMASK(_irqs_) \
outw(INTC_BASE + IRQER_OFFSET, \
inw(INTC_BASE + IRQER_OFFSET) | (_irqs_))
#define HAL_INTC_IRQ_CLEAR(_irqs_) \
outw(INTC_BASE + IRQICR_OFFSET, (_irqs_))
#define HAL_INTC_FIQ_CONFIGURE(_irqs_, _edge_, _falling_) \
HAL_INTC_IRQ_CONFIGURE(_irqs_, _edge_, _falling_)
#define HAL_INTC_FIQ_MASK(_irqs_) HAL_INTC_IRQ_MASK(_irqs_)
#define HAL_INTC_FIQ_UNMASK(_irqs_) HAL_INTC_IRQ_UNMASK(_irqs_)
#define HAL_INTC_FIQ_CLEAR(_irqs_) HAL_INTC_IRQ_CLEAR(_irqs_)
/************************************
* HAL Level : Timer *
************************************/
#define HAL_TIMER_INITIALIZE() \
do { \
outw(TM_CR, 0); \
outw(TM_MTCH1(0), 0); \
outw(TM_MTCH1(1), 0); \
outw(TM_MTCH1(2), 0); \
outw(TM_MSK, 0); \
outw(TM_STA, 0xFFFFFFFF); \
outw(TM_STA, 0); \
} while(0)
#define HAL_TIMER_START(_tmr_) \
outw(TM_CR, inw(TM_CR) | (0x1 << (3 * (_tmr_))))
#define HAL_TIMER_STOP(_tmr_) \
outw(TM_CR, inw(TM_CR) & ~(0x1 << (3 * (_tmr_))))
#define HAL_TIMER_READ(_tmr_, _pvalue_) \
*(volatile unsigned int *)_pvalue_ = \
inw(TM_LOAD(_tmr_)) - inw(TM_CNTR(_tmr_))
#define HAL_TIMER_SET_PERIOD(_tmr_, _period_) \
do { \
outw(TM_LOAD(_tmr_), _period_); \
outw(TM_CNTR(_tmr_), _period_); \
} while(0)
#define HAL_TIMER_IRQ_ENABLE(_tmr_, _ie_) \
do { \
if(_ie_) \
outw(TM_MSK, inw(TM_MSK) & ~(0x1 << (3 * (_tmr_))));\
else \
outw(TM_MSK, inw(TM_MSK) | (0x1 << (3 * (_tmr_)))); \
} while(0)
#define HAL_TIMER_IRQ_STATUS(_tmr_, _pvalue_) \
*(volatile unsigned int *)_pvalue_ = \
(inw(TM_STA) & (0x7 << (3 * (_tmr_))))
#define HAL_TIMER_IRQ_CLR(_tmr_) \
outw(TM_STA, (0x7 << (3 * (_tmr_))))
/************************************
* HAL Level : GPIO *
************************************/
#define HAL_GPIO_INITIALIZE(_pin_) \
do { \
outw(GPIO_BASE + GPIO_DIR_OFFSET, \
inw(GPIO_BASE + GPIO_DIR_OFFSET) & ~_pin_); \
outw(GPIO_BASE + GPIO_IR_OFFSET, \
inw(GPIO_BASE + GPIO_IR_OFFSET) | _pin_); \
outw(GPIO_BASE + GPIO_DCLEAR_OFFSET, -1); \
outw(GPIO_BASE + GPIO_BPS_OFFSET, 0x0000FFFF); \
outw(GPIO_BASE + GPIO_BE_OFFSET, _pin_); \
outw(GPIO_BASE + GPIO_IC_OFFSET, -1); \
outw(GPIO_BASE + GPIO_IE_OFFSET, _pin_); \
} while(0)
#define HAL_GPIO_READ() inw(GPIO_BASE + GPIO_DIN_OFFSET)
#define HAL_GPIO_IRQ_CLR(_pin_) outw(GPIO_BASE + GPIO_IC_OFFSET, _pin_)
#ifdef __ASSEMBLY__
/************************************
* HAL : AG102 defined vectors *
************************************/
.macro hal_hw_vectors
vector Interrupt_HW0 // (9) Interrupt HW0 (for IVB.IVIC_VER = 0, FIR)
vector Interrupt_HW1 // (10) Interrupt HW1 (for IVB.IVIC_VER = 0, IRQ)
vector Interrupt_UNDEF // (11) Interrupt HW2
vector Interrupt_UNDEF // (12) Interrupt HW3
vector Interrupt_UNDEF // (13) Interrupt HW4
vector Interrupt_UNDEF // (14) Interrupt HW5
vector Interrupt_HW6 // (15) Interrupt HW6 (for IVB.IVIC_VER = 0, SW0)
.endm
.macro hal_hw_ISR
Os_Trap_Interrupt_HW HW0_FIQ
Os_Trap_Interrupt_HW HW1_IRQ
Os_Trap_Interrupt_HW HW6_SW0
.endm
.macro hal_set_led, val
.endm
#endif /* _ASSEMBLY__ */
#endif /* AG102_REGS */
demo-int-new-ivbase/src/assert_demos.h 0000644 0 0 1234 12415051334 16012 0 ustar 00nobody nobody #ifndef ASSERT_DEMOS_H
#define ASSERT_DEMOS_H
#ifdef USE_C_EXT
//#ifdef ASSERT_V3M_ONLY
#if !(defined(NDS32_BASELINE_V3) || defined(NDS32_BASELINE_V3M))
#error USE_C_EXT is only supported by NDS32_BASELINE_V3/NDS32_BASELINE_V3M tool-chain!
#endif
#endif //#ifdef USE_C_EXT
#ifdef NDS32_BASELINE_V3M
//#ifdef ASSERT_16MB_ONLY
#ifndef CFG_16MB
#error NDS32_BASELINE_V3M tool-chain only supports CFG_16MB (24-bit address)!
#endif
#endif //#ifdef NDS32_BASELINE_V3M
#ifdef DEMO_CACHE
#ifdef NDS32_BASELINE_V3M
#error NDS32_BASELINE_V3M tool-chain supports no CCTL by the demo implemented!
#endif
#endif //#ifdef DEMO_CACHE
#endif //#ifdef ASSERT_DEMOS_H
demo-int-new-ivbase/src/config.h 0000644 0 0 4726 12415625050 14602 0 ustar 00nobody nobody /*
* Config the features of startup demo programs.
*/
#ifndef __CONFIG_H__
#define __CONFIG_H__
// Please put the defines shared by makefile projects and AndeSight projects
#ifndef CFG_MAKEFILE
// The defines are only used by AndeSight projects
//----------------------------------------------------------------------------------------------------
// Users can configure the defines in this area
// to match different environment setting
//#define CFG_16MB // platform is 16MB, if it isn't defined, platform is 4GB
//#define CFG_AG102 // platform is AG102
//#define CFG_AE210P // platform is AE210P
#define CFG_AG101P // platform is AG101P
#define BUILD_MODE BUILD_SIMU // NOTE: AE210P support BUILD_XIP only
//----------------------------------------------------------------------------------------------------
// The followings are predefined settings
// Please do not modify them
#define BUILD_LOAD 1 // The program is loaded by GDB or eBIOS
#define BUILD_BURN 2 // The program is burned to the flash, but run in RAM
// demo-ls2 use BURN mode
#define BUILD_XIP 3 // The program is burned to the flash and run in the flash
// To use this mode, xip linker script files must be used
// demo-ls1 use XIP mode
#define BUILD_SIMU 4 // The program is run in the simulation environment
#ifdef DEMO_LS1
// demo-ls1 needs to use the XIP mode
#undef BUILD_MODE
#define BUILD_MODE BUILD_XIP
#endif
#ifdef DEMO_LS2
// demo-ls2 needs to use the BURN mode
#undef BUILD_MODE
#define BUILD_MODE BUILD_BURN
#endif
#ifdef DEMO_LS3
// demo-ls3 needs to use the XIP mode without RAM
#undef BUILD_MODE
#define BUILD_MODE BUILD_XIP
#define CFG_NORAM
#endif
#ifndef NDS32_EXT_EX9
// This toolchain cannot support EX9
#define CONFIG_NO_NDS32_EXT_EX9
#endif
#if BUILD_MODE == BUILD_BURN
// Burn mode
#define CFG_LLINIT // do low level init
#define CFG_REMAP // do remap
#elif BUILD_MODE == BUILD_XIP
// XIP mode
#define CFG_LLINIT // do low level init
#elif BUILD_MODE == BUILD_SIMU
// Simu mode
#define CFG_SIMU
#define CFG_LLINIT // do low level init
#else
// Load mode
#endif
#ifdef NDS32_BASELINE_V3M
// v3m toolchain only support 16MB
#undef CFG_16MB
#define CFG_16MB
#endif
// Platform configure check
#ifdef CFG_AG102
#ifdef CFG_16MB
#error "AG102 does NOT supports CFG_16MB"
#endif
#endif
#ifdef CFG_AE210P
#if BUILD_MODE != BUILD_XIP
#error "AE210P supports BUILD_XIP only"
#endif
#endif
#endif // CFG_MAKEFILE
#endif // __CONFIG_H__
demo-int-new-ivbase/src/crt0.S 0000644 0 0 16105 12415637450 14241 0 ustar 00nobody nobody ##==============================================================================
##
## crt0.S
##
## nds32 startup code
##
##==============================================================================
##
## Copyright (c) 1995, 1996, 1997, 1998 Cygnus Solutions
##
## The authors hereby grant permission to use, copy, modify, distribute,
## and license this software and its documentation for any purpose, provided
## that existing copyright notices are retained in all copies and that this
## notice is included verbatim in any distributions. No written agreement,
## license, or royalty fee is required for any of the authorized uses.
## Modifications to this software may be copyrighted by their authors
## and need not follow the licensing terms described here, provided that
## the new terms are clearly indicated on the first page of each file where
## they apply.
##
#include "config.h"
#include "interrupt.h"
#if defined(CFG_AG102)
#include "ag102.h"
#elif defined(CFG_AE210P)
#include "ae210p.h"
#else
#include "ag101p.h"
#endif
##------------------------------------------------------------------------------
.macro vector name
.align 2
j OS_Trap_\name
.endm
.macro OS_Trap_Interrupt_HW num
OS_Trap_Interrupt_HW\num:
push $r0
li $r0, \num
b common_ISR_NEW_wrapper
.endm
.macro OS_Trap_Interrupt_NEW_HW num
OS_Trap_Interrupt_NEW_HW\num:
push $r0
li $r0, \num
b common_ISR_NEW_wrapper
.endm
.macro LED x
hal_set_led \x
.endm
.section .nds32_init, "ax"
!========================================================================
! Vector table
!========================================================================
.align 2
exception_vector:
j _start ! (0) Trap Reset
vector TLB_Fill ! (1) Trap TLB fill
vector PTE_Not_Present ! (2) Trap PTE not present
vector TLB_Misc ! (3) Trap TLB misc
vector TLB_VLPT_Miss ! (4) Trap TLB VLPT miss
vector Machine_Error ! (5) Trap Machine error
vector Debug_Related ! (6) Trap Debug related
vector General_Exception ! (7) Trap General exception
vector Syscall ! (8) Syscall
/* HW interrupt vector layout */
hal_hw_vectors
.align 2
exception_vector_end:
exception_handler:
.long tlb_exception_handler
.long error_exception_handler
.long syscall_handler
ISR_TABLE:
.long HW0_ISR
.long HW1_ISR
.long HW2_ISR
.long HW3_ISR
.long HW4_ISR
.long HW5_ISR
.long HW6_ISR
.long HW7_ISR
.long HW8_ISR
.long HW9_ISR
.long HW10_ISR
.long HW11_ISR
.long HW12_ISR
.long HW13_ISR
.long HW14_ISR
.long HW15_ISR
.long HW16_ISR
.long HW17_ISR
.long HW18_ISR
.long HW19_ISR
.long HW20_ISR
.long HW21_ISR
.long HW22_ISR
.long HW23_ISR
.long HW24_ISR
.long HW25_ISR
.long HW26_ISR
.long HW27_ISR
.long HW28_ISR
.long HW29_ISR
.long HW30_ISR
.long HW31_ISR
/*
* exception handlers
*/
/*----------------------------------------------------------------------
Since N903 doesn't have MMU, make them share the common error handler.
----------------------------------------------------------------------*/
OS_Trap_TLB_Fill:
/*
SAVE_ALL
li $r0, #0x1
b tlb_exception_handler
*/
OS_Trap_PTE_Not_Present:
/*
SAVE_ALL
li $r0, #0x2
b tlb_exception_handler
*/
OS_Trap_TLB_Misc:
/*
SAVE_ALL
li $r0, #0x3
b tlb_exception_handler
*/
OS_Trap_TLB_VLPT_Miss:
1: b 1b
SAVE_ALL
// li $r0, #0x4
b tlb_exception_handler
OS_Trap_Machine_Error:
1: b 1b
SAVE_ALL
li $r0, #0x5
b error_exception_handler
OS_Trap_Debug_Related:
1: b 1b
SAVE_ALL
li $r0, #0x6
b error_exception_handler
OS_Trap_General_Exception:
1: b 1b
SAVE_ALL
li $r0, #0x7
b error_exception_handler
OS_Trap_Syscall:
SYSCALL_SAVE_ALL
bal syscall_handler
SYSCALL_RESTORE_ALL
iret
OS_Trap_Interrupt_UNDEF:
push $r0
li $r0, 0xff
b common_ISR_wrapper
/* Other HW interrupt handlers */
hal_hw_ISR
common_ISR_wrapper:
SAVE_ALL_HW
la $r1, ISR_TABLE
lw $r1, [$r1+$r0<<2]
jral $r1
RESTORE_ALL_HW
iret
/* hujin new vector table
*/
.section .nds32_aa, "ax"
!========================================================================
! Vector table
!========================================================================
.align 2
new_exception_vector:
j _start ! (0) Trap Reset
vector TLB_Fill ! (1) Trap TLB fill
vector PTE_Not_Present ! (2) Trap PTE not present
vector TLB_Misc ! (3) Trap TLB misc
vector TLB_VLPT_Miss ! (4) Trap TLB VLPT miss
vector Machine_Error ! (5) Trap Machine error
vector Debug_Related ! (6) Trap Debug related
vector General_Exception ! (7) Trap General exception
vector Syscall ! (8) Syscall
/* HW interrupt vector layout */
hal_hw_new_vectors
.align 2
new_exception_vector_end:
new_exception_handler:
.long tlb_exception_handler
.long error_exception_handler
.long syscall_handler
NEW_ISR_TABLE:
.long HW0_ISR
.long NEW_HW1_ISR
.long HW2_ISR
.long HW3_ISR
.long HW4_ISR
.long HW5_ISR
.long HW6_ISR
.long HW7_ISR
.long HW8_ISR
.long HW9_ISR
.long HW10_ISR
.long HW11_ISR
.long HW12_ISR
.long HW13_ISR
.long HW14_ISR
.long HW15_ISR
.long HW16_ISR
.long HW17_ISR
.long HW18_ISR
.long HW19_ISR
.long HW20_ISR
.long HW21_ISR
.long HW22_ISR
.long HW23_ISR
.long HW24_ISR
.long HW25_ISR
.long HW26_ISR
.long HW27_ISR
.long HW28_ISR
.long HW29_ISR
.long HW30_ISR
.long HW31_ISR
/*
* exception handlers
*/
/* new Other HW interrupt handlers */
hal_hw_new_ISR
common_ISR_NEW_wrapper:
SAVE_ALL_HW
la $r1, NEW_ISR_TABLE
lw $r1, [$r1+$r0<<2]
jral $r1
RESTORE_ALL_HW
iret
##------------------------------------------------------------------------------
## Startup code
#ifdef CFG_LLINIT
#ifdef CFG_REMAP
#define LED_VALUE (0x66) //Burn
#else
#define LED_VALUE (0x11) //xIp
#endif
#else
#define LED_VALUE (0x00) //lOad
#endif
.section .text
.global _start
.weak _call_exit
.weak _SDA_BASE_
.weak _FP_BASE_
.func _start
.type _start, @function
.align 2
_start:
!************************** Begin of do-not-modify **************************
! Please don� modify this code
! Initialize the registers used by the compiler
#ifndef CONFIG_NO_NDS32_EXT_EX9
! make sure the instruction before setting ITB
! will not be optimized with ex9
.no_ex9_begin ! disable ex9 generation
#endif
! Support Relax, Set $gp to _SDA_BASE_
la $gp, _SDA_BASE_ ! init GP for small data access
#ifdef CFG_DEBUG
mfsr $r0, $MSC_CFG
#ifndef CONFIG_NO_NDS32_EXT_EX9
li $r1, (1 << 24) ! EIT
and $r2, $r0, $r1
1: beqz $r2, 1b
#endif
#ifdef __NDS32_EXT_IFC__
li $r1, (1 << 19) ! IFC
and $r2, $r0, $r1
1: beqz $r2, 1b
#endif
#endif //#ifdef CFG_DEBUG
#ifndef CONFIG_NO_NDS32_EXT_EX9
! Initialize the table base of EX9 instruction
la $r0, _ITB_BASE_ ! init ITB
mtusr $r0, $ITB
.no_ex9_end
#endif
!*************************** End of do-not-modify ***************************
la $fp, _FP_BASE_ ! init FP
la $sp, _stack ! init SP
#ifndef CFG_SIMU
! light LED
LED LED_VALUE
#endif
#ifdef CFG_LLINIT
bal _nds32_init_mem
#endif
bal __init
bal main
1: b 1b
.size _start, .-_start
.end
demo-int-new-ivbase/src/init-default.c 0000644 0 0 17544 12415636322 16003 0 ustar 00nobody nobody #include
#include "config.h"
#include "assert_demos.h"
/* It will use Default_Handler if you don't have one */
#pragma weak tlb_exception_handler = Default_Handler
#pragma weak error_exception_handler = Default_Handler
#pragma weak syscall_handler = Default_Handler
#pragma weak HW0_ISR = Default_Handler
#pragma weak HW1_ISR = Default_Handler
#pragma weak NEW_HW1_ISR = Default_Handler
#pragma weak HW2_ISR = Default_Handler
#pragma weak HW3_ISR = Default_Handler
#pragma weak HW4_ISR = Default_Handler
#pragma weak HW5_ISR = Default_Handler
#pragma weak HW6_ISR = Default_Handler
#pragma weak HW7_ISR = Default_Handler
#pragma weak HW8_ISR = Default_Handler
#pragma weak HW9_ISR = Default_Handler
#pragma weak HW10_ISR = Default_Handler
#pragma weak HW11_ISR = Default_Handler
#pragma weak HW12_ISR = Default_Handler
#pragma weak HW13_ISR = Default_Handler
#pragma weak HW14_ISR = Default_Handler
#pragma weak HW15_ISR = Default_Handler
#pragma weak HW16_ISR = Default_Handler
#pragma weak HW17_ISR = Default_Handler
#pragma weak HW18_ISR = Default_Handler
#pragma weak HW19_ISR = Default_Handler
#pragma weak HW20_ISR = Default_Handler
#pragma weak HW21_ISR = Default_Handler
#pragma weak HW22_ISR = Default_Handler
#pragma weak HW23_ISR = Default_Handler
#pragma weak HW24_ISR = Default_Handler
#pragma weak HW25_ISR = Default_Handler
#pragma weak HW26_ISR = Default_Handler
#pragma weak HW27_ISR = Default_Handler
#pragma weak HW28_ISR = Default_Handler
#pragma weak HW29_ISR = Default_Handler
#pragma weak HW30_ISR = Default_Handler
#pragma weak HW31_ISR = Default_Handler
#pragma weak SW0_ISR = Default_Handler
#pragma weak VEP0_ISR = Default_Handler
#pragma weak VEP1_ISR = Default_Handler
#pragma weak VEP2_ISR = Default_Handler
#pragma weak VEP3_ISR = Default_Handler
#pragma weak VEP4_ISR = Default_Handler
#pragma weak VEP5_ISR = Default_Handler
#pragma weak VEP6_ISR = Default_Handler
#pragma weak VEP7_ISR = Default_Handler
#pragma weak VEP8_ISR = Default_Handler
#pragma weak VEP9_ISR = Default_Handler
#pragma weak VEP10_ISR = Default_Handler
#pragma weak VEP11_ISR = Default_Handler
#pragma weak VEP12_ISR = Default_Handler
#pragma weak VEP13_ISR = Default_Handler
#pragma weak VEP14_ISR = Default_Handler
#pragma weak VEP15_ISR = Default_Handler
#pragma weak VEP16_ISR = Default_Handler
#pragma weak VEP17_ISR = Default_Handler
#pragma weak VEP18_ISR = Default_Handler
#pragma weak VEP19_ISR = Default_Handler
#pragma weak VEP20_ISR = Default_Handler
#pragma weak VEP21_ISR = Default_Handler
#pragma weak VEP22_ISR = Default_Handler
#pragma weak VEP23_ISR = Default_Handler
#pragma weak VEP24_ISR = Default_Handler
#pragma weak VEP25_ISR = Default_Handler
#pragma weak VEP26_ISR = Default_Handler
#pragma weak VEP27_ISR = Default_Handler
#pragma weak VEP28_ISR = Default_Handler
#pragma weak VEP29_ISR = Default_Handler
#pragma weak VEP30_ISR = Default_Handler
#pragma weak VEP31_ISR = Default_Handler
#pragma weak VEP32_ISR = Default_Handler
#pragma weak VEP33_ISR = Default_Handler
#pragma weak VEP34_ISR = Default_Handler
#pragma weak VEP35_ISR = Default_Handler
#pragma weak VEP36_ISR = Default_Handler
#pragma weak VEP37_ISR = Default_Handler
#pragma weak VEP38_ISR = Default_Handler
#pragma weak VEP39_ISR = Default_Handler
#pragma weak VEP40_ISR = Default_Handler
#pragma weak VEP41_ISR = Default_Handler
#pragma weak VEP42_ISR = Default_Handler
#pragma weak VEP43_ISR = Default_Handler
#pragma weak VEP44_ISR = Default_Handler
#pragma weak VEP45_ISR = Default_Handler
#pragma weak VEP46_ISR = Default_Handler
#pragma weak VEP47_ISR = Default_Handler
#pragma weak VEP48_ISR = Default_Handler
#pragma weak VEP49_ISR = Default_Handler
#pragma weak VEP50_ISR = Default_Handler
#pragma weak VEP51_ISR = Default_Handler
#pragma weak VEP52_ISR = Default_Handler
#pragma weak VEP53_ISR = Default_Handler
#pragma weak VEP54_ISR = Default_Handler
#pragma weak VEP55_ISR = Default_Handler
#pragma weak VEP56_ISR = Default_Handler
#pragma weak VEP57_ISR = Default_Handler
#pragma weak VEP58_ISR = Default_Handler
#pragma weak VEP59_ISR = Default_Handler
#pragma weak VEP60_ISR = Default_Handler
#pragma weak VEP61_ISR = Default_Handler
#pragma weak VEP62_ISR = Default_Handler
#pragma weak VEP63_ISR = Default_Handler
int uart_puts(const char *);
__attribute__((unused))
static void Default_Handler()
{
uart_puts("Default Handler");
while (1) ;
}
#pragma weak __soc_init = __null_function
void __null_function()
{;
}
void __c_init()
{
/* Use compiler builtin memcpy and memset */
#define MEMCPY(des, src, n) __builtin_memcpy ((des), (src), (n))
#define MEMSET(s, c, n) __builtin_memset ((s), (c), (n))
extern char _end;
extern char __bss_start;
int size;
/* If we load code to RAM we don't need to copy
* data section and lma will be equal to vma.
* */
#if defined(CFG_LLINIT) && !defined(CFG_REMAP) && !defined(CFG_SIMU)
/* data section will be copied before we remap.
* We don't need to copy data section here. */
extern char __data_lmastart;
extern char __data_start;
extern char _edata;
/* Copy data section to RAM */
size = &_edata - &__data_start;
MEMCPY(&__data_start, &__data_lmastart, size);
#endif
/* Clear bss section */
size = &_end - &__bss_start;
MEMSET(&__bss_start, 0, size);
return;
}
void __attribute__ ((optimize("Os"))) __cpu_init()
{
unsigned int tmp;
/* turn on BTB */
tmp = 0x0;
__nds32__mtsr(tmp, NDS32_SR_MISC_CTL);
/* disable all hardware interrupts */
__nds32__mtsr(0x0, NDS32_SR_INT_MASK);
#if (defined(NDS32_BASELINE_V3M) || defined(NDS32_BASELINE_V3))
if (__nds32__mfsr(NDS32_SR_IVB) & 0x01)
__nds32__mtsr(0x0, NDS32_SR_INT_MASK);
#endif
#if defined(CFG_EVIC)
/* set EVIC, vector size: 4 bytes, base: 0x0 */
__nds32__mtsr(0x1<<13, NDS32_SR_IVB);
#else
# if defined(USE_C_EXT)
/* If we use v3/v3m toolchain and want to use
* C extension please use USE_C_EXT in CFLAGS
*/
#ifdef NDS32_BASELINE_V3
/* set IVIC, vector size: 4 bytes, base: 0x0 */
__nds32__mtsr(0x0, NDS32_SR_IVB);
#else
/* set IVIC, vector size: 16 bytes, base: 0x0 */
__nds32__mtsr(0x1<<14, NDS32_SR_IVB);
#endif
# else
/* set IVIC, vector size: 4 bytes, base: 0x0
* If we use v3/v3m toolchain and want to use
* assembly version please don't use USE_C_EXT
* in CFLAGS */
__nds32__mtsr(0x0, NDS32_SR_IVB);
# endif
#endif
/* Set PSW INTL to 0 */
tmp = __nds32__mfsr(NDS32_SR_PSW);
tmp = tmp & 0xfffffff9;
#if (defined(NDS32_BASELINE_V3M) || defined(NDS32_BASELINE_V3))
/* Set PSW CPL to 7 to allow any priority */
tmp = tmp | 0x70008;
#endif
__nds32__mtsr(tmp, NDS32_SR_PSW);
__nds32__dsb();
#if (defined(NDS32_BASELINE_V3M) || defined(NDS32_BASELINE_V3))
/* Check interrupt priority programmable*
* IVB.PROG_PRI_LVL
* 0: Fixed priority -- no exist ir18 1r19
* 1: Programmable priority
*/
if (__nds32__mfsr(NDS32_SR_IVB) & 0x01) {
/* Set PPL2FIX_EN to 0 to enable Programmable
* Priority Level */
__nds32__mtsr(0x0, NDS32_SR_INT_CTRL);
/* Check IVIC numbers (IVB.NIVIC) */
if ((__nds32__mfsr(NDS32_SR_IVB) & 0x0E)>>1 == 5) { // 32IVIC
/* set priority HW9: 0, HW13: 1, HW19: 2,
* HW#-: 0 */
__nds32__mtsr(0x04000000, NDS32_SR_INT_PRI);
__nds32__mtsr(0x00000080, NDS32_SR_INT_PRI2);
} else {
/* set priority HW0: 0, HW1: 1, HW2: 2, HW3: 3
* HW4-: 0 */
__nds32__mtsr(0x000000e4, NDS32_SR_INT_PRI);
}
}
#endif
/* enable FPU if the CPU support FPU */
#if defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)
tmp = __nds32__mfsr(NDS32_SR_FUCOP_EXIST);
if ((tmp & 0x80000001) == 0x80000001) {
tmp = __nds32__mfsr(NDS32_SR_FUCOP_CTL);
__nds32__mtsr((tmp | 0x1), NDS32_SR_FUCOP_CTL);
}
#endif
return;
}
void __soc_init();
void __init()
{
/*----------------------------------------------------------
!! Users should NOT add any code before this comment !!
------------------------------------------------------------*/
__cpu_init();
__c_init(); //copy data section, clean bss
__soc_init();
}
demo-int-new-ivbase/src/init-soc.c 0000644 0 0 3577 12415051334 15056 0 ustar 00nobody nobody /*
This file includes weak (i.e. optional) functions to perform SoC related
initialization. They are:
1). _nds32_init_mem():
Executed before C language initialization to make memory
ready so that program data can be initialized. An example
is to initialize DRAM.
Since this is called before C initialization, please
use provided macros to avoid problems.
2). __soc_init():
Further SoC intialization. Called after C language
initialization, so it is a typical C function.
*/
#include
#include "config.h"
#if defined(CFG_AG102)
#include "ag102.h"
#elif defined(CFG_AE210P)
#include "ae210p.h"
#else
#include "ag101p.h"
#endif
#ifdef CFG_LLINIT
/* This must be a leave function, no child funcion. */
void _nds32_init_mem(void) __attribute__((no_prologue, optimize("Os")));
void _nds32_init_mem(void) //The function is weak (optional)
{
#ifndef CFG_NORAM
HAL_MEMORY_SETUP(ORIG_RAM_BASE);
#ifdef CFG_REMAP
/* remap */
extern char _edata;
/* relocation, copy ROM code to SDRAM */
NDS32_FMEMCPY(ORIG_RAM_BASE, 0x0, &_edata);
HAL_MEMORY_REMAP();
__nds32__isb();
HAL_MEMORY_REMAP_ADJUST();
#endif // CFG_REMAP
#else
#if !defined(CFG_REMAP) && !defined(CFG_SIMU)
/* System without RAM. Use data local memory as system memory. */
extern char __data_start;
register unsigned int dlmsize;
dlmsize = 0x1000 << ((__nds32__mfsr(NDS32_SR_DLMB) >> 1) & 0xf);
/* Set DLM base to .data start address and enable it */
__nds32__mtsr((unsigned)&__data_start|1, NDS32_SR_DLMB);
__nds32__dsb();
/* Update stack pointer to end of DLM
* We suppose the .data + .bss + stack less then DLM size */
__nds32__set_current_sp((unsigned)&__data_start + dlmsize);
#endif
#endif
}
#endif
void __soc_init() //The function is weak (optional)
{
#ifdef CFG_LLINIT
void uart_init(void);
uart_init();
#endif
}
demo-int-new-ivbase/src/interrupt.c 0000644 0 0 17375 12415634740 15456 0 ustar 00nobody nobody #include
#include "config.h"
#if defined(CFG_AG102)
#include "ag102.h"
#elif defined(CFG_AE210P)
#include "ae210p.h"
#else
#include "ag101p.h"
#endif
extern int uart_puts(const char *s);
inline void GIE_ENABLE()
{
__nds32__setgie_en();
}
inline void GIE_DISABLE()
{
__nds32__setgie_dis();
__nds32__dsb();
}
/* this function generates a s/w interrupt */
void gen_swi()
{
unsigned int int_pend;
int_pend = __nds32__mfsr(NDS32_SR_INT_PEND);
int_pend |= 0x10000;
__nds32__mtsr(int_pend, NDS32_SR_INT_PEND);
__nds32__dsb();
}
/* Set the corresponding IRQ source to be routed to HW vector. */
void setIRQ_ivic(unsigned int vector, int hw)
{
HAL_INTC_HWIRQ_ROUTE(vector, hw);
}
void enableIntr(unsigned int mask, int edge, int neg)
{
HAL_INTC_IRQ_CONFIGURE(mask, edge, neg);
HAL_INTC_IRQ_UNMASK(mask);
}
void enableFiqIntr(unsigned int mask, int edge, int neg)
{
HAL_INTC_FIQ_CONFIGURE(mask, edge, neg);
HAL_INTC_FIQ_UNMASK(mask);
}
#define TICK_HZ 1
#ifdef CFG_SIMU
#define SIMU_FACTOR (8)
#else
#define SIMU_FACTOR (0)
#endif
#define TIMER1 0
#define TIMER2 1
#define TIMER3 2
void Tmr_TickInit()
{
/* timer1 will interrupt in every 4 secs */
unsigned int period = (4 * (PCLKFREQ / TICK_HZ)) >> SIMU_FACTOR;
/* Initialize all Timers */
HAL_TIMER_INITIALIZE();
/* Start Timer1 with interrupt enabled */
HAL_TIMER_SET_PERIOD(TIMER1, period);
HAL_TIMER_IRQ_ENABLE(TIMER1, 1);
HAL_TIMER_START(TIMER1);
}
void intc_reset()
{
HAL_INTC_IRQ_MASK(0xFFFFFFFF);
HAL_INTC_IRQ_CLEAR(0xFFFFFFFF);
HAL_INTC_FIQ_MASK(0xFFFFFFFF);
HAL_INTC_FIQ_CLEAR(0xFFFFFFFF);
}
void initIntr()
{
/* Init GPIO */
HAL_GPIO_INITIALIZE(GPIO_USED_MASK);
/* Init timer */
Tmr_TickInit();
/* Check IVIC numbers (IVB.NIVIC) */
if ((__nds32__mfsr(NDS32_SR_IVB) & 0x0E) != 0) { // 32IVIC
#if (defined(NDS32_BASELINE_V3) || defined(NDS32_BASELINE_V3M))
/* set TIMER1 priority to low */
#if IRQ_TIMER1 < 16
__nds32__mtsr(1 << (IRQ_TIMER1 * 2), NDS32_SR_INT_PRI);
#else
__nds32__mtsr(1 << ((IRQ_TIMER1 - 16) * 2), NDS32_SR_INT_PRI2);
#endif
/* enable HW# (timer1, GPIO & SWI) */
__nds32__mtsr(IC_TIMER1 | IC_GPIO | IC_SWI, NDS32_SR_INT_MASK2);
/* Interrupt pending register, write 1 to clear */
__nds32__mtsr(0xFFFFFFFF, NDS32_SR_INT_PEND2);
#endif
} else {
/* Interrupt controller */
intc_reset();
/* IRQ source to be routed to HW0/HW1 */
setIRQ_ivic(IRQ_TIMER1, 1);
setIRQ_ivic(IRQ_GPIO, 0);
/* Timer is edge-trigger and falling-edge */
enableIntr(IC_TIMER1, 1, 0);
/* GPIO is level-trigger and active-high */
enableFiqIntr(IC_GPIO, 0, 0);
/* enable SW0, HW0 and HW1 */
__nds32__mtsr(0x10003, NDS32_SR_INT_MASK);
}
}
void initIntr_standby()
{
/* Init GPIO */
HAL_GPIO_INITIALIZE(GPIO_USED_MASK);
/* Check IVIC numbers (IVB.NIVIC) */
if ((__nds32__mfsr(NDS32_SR_IVB) & 0x0E) != 0) { // 32IVIC
#if (defined(NDS32_BASELINE_V3) || defined(NDS32_BASELINE_V3M))
/* enable HW (GPIO) */
__nds32__mtsr(IC_GPIO, NDS32_SR_INT_MASK2);
/* Interrupt pending register, write 1 to clear */
__nds32__mtsr(0xFFFFFFFF, NDS32_SR_INT_PEND2);
#endif
} else {
/* Reset interrupt controller */
intc_reset();
/* GPIO source to be routed to HW0 */
setIRQ_ivic(IRQ_GPIO, 0);
/* GPIO is level-trigger and active-high */
enableFiqIntr(IC_GPIO, 0, 0);
/* enable HW0 */
__nds32__mtsr(0x0001, NDS32_SR_INT_MASK);
}
}
void clear_swi()
{
unsigned int int_pend;
int_pend = 0x10;
__nds32__mtsr(int_pend, NDS32_SR_INT_PEND);
__nds32__dsb();
}
#if (defined(FIQ_ISR) && defined(IRQ_ISR))
/* HW0, HW1 and SW0 interrupts will only occur on IVIC version (IVB.IVIC_VER) = 0. */
void FIQ_ISR()
{
uart_puts("* Enter HW0 ISR with GPIO *\n");
HAL_GPIO_IRQ_CLR(0xFFFFFFFF);
/* This service will take 6 secs */
unsigned int period;
period = (6 * (PCLKFREQ / TICK_HZ)) >> SIMU_FACTOR;
HAL_TIMER_SET_PERIOD(TIMER2, period << 1);
HAL_TIMER_START(TIMER2);
while (1) {
unsigned int tm2_cntr;
HAL_TIMER_READ(TIMER2, &tm2_cntr);
if (tm2_cntr > period)
break;
}
HAL_TIMER_STOP(TIMER2);
uart_puts("* End of HW0 ISR it takes 6 secs *\n");
}
void IRQ_ISR()
{
uart_puts("* Enter HW1 ISR, It comes in every 4 secs. *\n");
/* Unmask Timer interrupt and clear */
HAL_INTC_IRQ_MASK(IC_TIMER1);
HAL_INTC_IRQ_CLEAR(IC_TIMER1);
/* Clear Timer1 interrupt status */
HAL_TIMER_IRQ_CLR(TIMER1);
uart_puts("* Top-Half of HW1 is done. Enable GIE *\n");
GIE_ENABLE();
/* This service will take 2 secs */
unsigned int period;
period = (2 * (PCLKFREQ / TICK_HZ)) >> SIMU_FACTOR;
HAL_TIMER_SET_PERIOD(TIMER3, period << 1);
HAL_TIMER_START(TIMER3);
while (1) {
unsigned int tm3_cntr;
HAL_TIMER_READ(TIMER3, &tm3_cntr);
if (tm3_cntr > period)
break;
}
HAL_TIMER_STOP(TIMER3);
uart_puts("* Bottom-Half of HW1 is done and it takes 2 secs. Enable it self.*\n");
/* Enable Timer Interrupt */
HAL_INTC_IRQ_UNMASK(IC_TIMER1);
}
void NEW_IRQ_ISR()
{
uart_puts("* Enter NEW HW1 ISR, It comes in every 4 secs. *\n");
/* Unmask Timer interrupt and clear */
HAL_INTC_IRQ_MASK(IC_TIMER1);
HAL_INTC_IRQ_CLEAR(IC_TIMER1);
/* Clear Timer1 interrupt status */
HAL_TIMER_IRQ_CLR(TIMER1);
uart_puts("* Top-Half of NEW HW1 is done. Enable GIE *\n");
GIE_ENABLE();
/* This service will take 2 secs */
unsigned int period;
period = (2 * (PCLKFREQ / TICK_HZ)) >> SIMU_FACTOR;
HAL_TIMER_SET_PERIOD(TIMER3, period << 1);
HAL_TIMER_START(TIMER3);
while (1) {
unsigned int tm3_cntr;
HAL_TIMER_READ(TIMER3, &tm3_cntr);
if (tm3_cntr > period)
break;
}
HAL_TIMER_STOP(TIMER3);
uart_puts("* Bottom-Half of NEW HW1 is done and it takes 2 secs. Enable it self.*\n");
/* Enable Timer Interrupt */
HAL_INTC_IRQ_UNMASK(IC_TIMER1);
}
#endif
void SW0_ISR()
{
uart_puts("A software interrupt occurs ...\n");
clear_swi();
return;
}
#if (defined(NDS32_BASELINE_V3) || defined(NDS32_BASELINE_V3M))
/* SW, GPIO and Timer hardware interrupt will only occur on IVIC version (IVB.IVIC_VER) = 1. */
void SWI_ISR(unsigned int num)
{
__nds32__mtsr((1 << num), NDS32_SR_INT_PEND2);
SW0_ISR();
}
void GPIO_ISR(unsigned int num)
{
unsigned int msk = (1 << num);
/* Mask and clear HW interrupt vector */
__nds32__mtsr(__nds32__mfsr(NDS32_SR_INT_MASK2) & ~msk, NDS32_SR_INT_MASK2);
__nds32__dsb();
__nds32__mtsr(msk, NDS32_SR_INT_PEND2);
uart_puts("* Enter GPIO ISR *\n");
HAL_GPIO_IRQ_CLR(0xFFFFFFFF);
GIE_ENABLE();
/* This service will take 6 secs */
unsigned int period;
period = (6 * (PCLKFREQ / TICK_HZ)) >> SIMU_FACTOR;
HAL_TIMER_SET_PERIOD(TIMER2, period << 1);
HAL_TIMER_START(TIMER2);
while (1) {
unsigned int tm2_cntr;
HAL_TIMER_READ(TIMER2, &tm2_cntr);
if (tm2_cntr > period)
break;
}
HAL_TIMER_STOP(TIMER2);
uart_puts("* End of GPIO ISR it takes 6 secs *\n");
/* Unmask HW interrupt vector */
GIE_DISABLE();
__nds32__mtsr(__nds32__mfsr(NDS32_SR_INT_MASK2) | msk, NDS32_SR_INT_MASK2);
}
void TIMER_ISR(unsigned int num)
{
unsigned int msk = (1 << num);
/* Mask and clear HW interrupt vector */
__nds32__mtsr(__nds32__mfsr(NDS32_SR_INT_MASK2) & ~msk, NDS32_SR_INT_MASK2);
__nds32__dsb();
__nds32__mtsr(msk, NDS32_SR_INT_PEND2);
uart_puts("* Enter Timer ISR, It comes in every 4 secs. *\n");
/* Clear HW/Timer1 interrupt status */
HAL_TIMER_IRQ_CLR(TIMER1);
uart_puts("* Top-Half of Timer ISR is done. Enable GIE *\n");
GIE_ENABLE();
/* This service will take 2 secs */
unsigned int period;
period = (2 * (PCLKFREQ / TICK_HZ)) >> SIMU_FACTOR;
HAL_TIMER_SET_PERIOD(TIMER3, period << 1);
HAL_TIMER_START(TIMER3);
while (1) {
unsigned int tm3_cntr;
HAL_TIMER_READ(TIMER3, &tm3_cntr);
if (tm3_cntr > period)
break;
}
HAL_TIMER_STOP(TIMER3);
uart_puts("* Bottom-Half of Timer ISR is done and it takes 2 secs. Enable it self.*\n");
/* Unmask HW interrupt vector */
GIE_DISABLE();
__nds32__mtsr(__nds32__mfsr(NDS32_SR_INT_MASK2) | msk, NDS32_SR_INT_MASK2);
}
#endif
demo-int-new-ivbase/src/interrupt.h 0000644 0 0 15362 12415051334 15445 0 ustar 00nobody nobody #ifndef INTERRUPT_H
#define INTERRUPT_H
.macro gie_disable
setgie.d
dsb
.endm
.macro gie_enable
setgie.e
.endm
/* align $sp to 8B boundary */
.macro align_sp_8 R0="$r2", R1="$r3"
move \R0, $sp !keep original $sp to be pushed
#if !defined(NDS32_BASELINE_V3M) || 1 //could be optimized out
#ifndef NDS32_EXT_PERF
andi \R1, $sp, #4 ! R1 = $sp.bit2 // 0 or 4
subri \R1, \R1, #4 ! R1 = 4 - R1 // 4 or 0
sub $sp, $sp, \R1 ! $sp -= R1 //-4 or 0
push \R0
#else
addi $sp, $sp, #-4 ! $sp -= 4
bclr $sp, $sp, #2 ! $sp.bit2 = 0
sw \R0, [$sp]
#endif
#endif
.endm
.macro push_d0d1 R0="$r2", R1="$r3", R2="$r4", R3="$r5"
#ifdef NDS32_DX_REGS
mfusr \R0, $d1.lo
mfusr \R1, $d1.hi
mfusr \R2, $d0.lo
mfusr \R3, $d0.hi
pushm \R0, \R3
#endif
.endm
.macro pop_d0d1 R0="$r2", R1="$r3", R2="$r4", R3="$r5"
#ifdef NDS32_DX_REGS
popm \R0, \R3
mtusr \R0, $d1.lo
mtusr \R1, $d1.hi
mtusr \R2, $d0.lo
mtusr \R3, $d0.hi
#endif
.endm
.macro push_ifc_lp R0="$r2"
#ifdef NDS32_EXT_IFC
mfusr \R0, $IFC_LP
push \R0
#endif
.endm
.macro pop_ifc_lp R0="$r2"
#ifdef NDS32_EXT_IFC
pop \R0
mtusr \R0, $IFC_LP
#endif
.endm
.macro SAVE_FPU_REGS_00
addi $sp, $sp, -8
fsdi.bi $fd2, [$sp], -8
fsdi.bi $fd1, [$sp], -8
fsdi $fd0, [$sp+0]
.endm
.macro SAVE_FPU_REGS_01
addi $sp, $sp, -8
fsdi.bi $fd6, [$sp], -8
fsdi.bi $fd4, [$sp], -8
fsdi.bi $fd2, [$sp], -8
fsdi.bi $fd1, [$sp], -8
fsdi $fd0, [$sp+0]
.endm
.macro SAVE_FPU_REGS_02
addi $sp, $sp, -8
fsdi.bi $fd14, [$sp], -8
fsdi.bi $fd12, [$sp], -8
fsdi.bi $fd10, [$sp], -8
fsdi.bi $fd8, [$sp], -8
fsdi.bi $fd6, [$sp], -8
fsdi.bi $fd4, [$sp], -8
fsdi.bi $fd2, [$sp], -8
fsdi.bi $fd1, [$sp], -8
fsdi $fd0, [$sp+0]
.endm
.macro SAVE_FPU_REGS_03
addi $sp, $sp, -8
fsdi.bi $fd30, [$sp], -8
fsdi.bi $fd28, [$sp], -8
fsdi.bi $fd26, [$sp], -8
fsdi.bi $fd24, [$sp], -8
fsdi.bi $fd22, [$sp], -8
fsdi.bi $fd20, [$sp], -8
fsdi.bi $fd18, [$sp], -8
fsdi.bi $fd16, [$sp], -8
fsdi.bi $fd14, [$sp], -8
fsdi.bi $fd12, [$sp], -8
fsdi.bi $fd10, [$sp], -8
fsdi.bi $fd8, [$sp], -8
fsdi.bi $fd6, [$sp], -8
fsdi.bi $fd4, [$sp], -8
fsdi.bi $fd2, [$sp], -8
fsdi.bi $fd1, [$sp], -8
fsdi $fd0, [$sp+0]
.endm
.macro push_fpu
#if defined(NDS32_EXT_FPU_CONFIG_0)
SAVE_FPU_REGS_00
#elif defined(NDS32_EXT_FPU_CONFIG_1)
SAVE_FPU_REGS_01
#elif defined(NDS32_EXT_FPU_CONFIG_2)
SAVE_FPU_REGS_02
#elif defined(NDS32_EXT_FPU_CONFIG_3)
SAVE_FPU_REGS_03
#else
#endif
.endm
.macro RESTORE_FPU_REGS_00
fldi.bi $fd0, [$sp], 8
fldi.bi $fd1, [$sp], 8
fldi.bi $fd2, [$sp], 8
.endm
.macro RESTORE_FPU_REGS_01
fldi.bi $fd0, [$sp], 8
fldi.bi $fd1, [$sp], 8
fldi.bi $fd2, [$sp], 8
fldi.bi $fd4, [$sp], 8
fldi.bi $fd6, [$sp], 8
.endm
.macro RESTORE_FPU_REGS_02
fldi.bi $fd0, [$sp], 8
fldi.bi $fd1, [$sp], 8
fldi.bi $fd2, [$sp], 8
fldi.bi $fd4, [$sp], 8
fldi.bi $fd6, [$sp], 8
fldi.bi $fd8, [$sp], 8
fldi.bi $fd10, [$sp], 8
fldi.bi $fd12, [$sp], 8
fldi.bi $fd14, [$sp], 8
.endm
.macro RESTORE_FPU_REGS_03
fldi.bi $fd0, [$sp], 8
fldi.bi $fd1, [$sp], 8
fldi.bi $fd2, [$sp], 8
fldi.bi $fd4, [$sp], 8
fldi.bi $fd6, [$sp], 8
fldi.bi $fd8, [$sp], 8
fldi.bi $fd10, [$sp], 8
fldi.bi $fd12, [$sp], 8
fldi.bi $fd14, [$sp], 8
fldi.bi $fd16, [$sp], 8
fldi.bi $fd18, [$sp], 8
fldi.bi $fd20, [$sp], 8
fldi.bi $fd22, [$sp], 8
fldi.bi $fd24, [$sp], 8
fldi.bi $fd26, [$sp], 8
fldi.bi $fd28, [$sp], 8
fldi.bi $fd30, [$sp], 8
.endm
.macro pop_fpu
#if defined(NDS32_EXT_FPU_CONFIG_0)
RESTORE_FPU_REGS_00
#elif defined(NDS32_EXT_FPU_CONFIG_1)
RESTORE_FPU_REGS_01
#elif defined(NDS32_EXT_FPU_CONFIG_2)
RESTORE_FPU_REGS_02
#elif defined(NDS32_EXT_FPU_CONFIG_3)
RESTORE_FPU_REGS_03
#else
#endif
.endm
.macro SAVE_ALL
pushm $r0, $r5
pushm $r15,$r30
push_d0d1
push_ifc_lp
mfsr $r0, $IPC
mfsr $r1, $IPSW
pushm $r0, $r1
/* Descend interrupt level */
mfsr $r0, $PSW
addi $r0, $r0, #-2
mtsr $r0, $PSW
dsb
align_sp_8
push_fpu
.endm
.macro RESTORE_ALL
pop_fpu
lwi $sp, [$sp]
popm $r0, $r1
mtsr $r0, $IPC
mtsr $r1, $IPSW
pop_ifc_lp
pop_d0d1
popm $r15,$r30
popm $r0, $r5
.endm
.macro SYSCALL_SAVE_ALL
pushm $r1, $r9 ! $r0 for return value,
pushm $r15,$r30 ! $r0 ~ $r5 are arguments, and
push_d0d1 "$r6","$r7","$r8","$r9" ! saved them in case ABI are not followed
push_ifc_lp "$r6" ! $r6 ~ $r9 are clobber-list
mfsr $r6, $IPC
addi $r6, $r6, 4
mfsr $r7, $IPSW
pushm $r6, $r7 ! save $ipc, $ipsw
/* Descend interrupt level */
mfsr $r6, $PSW
addi $r6, $r6, #-2
mtsr $r6, $PSW
dsb
align_sp_8 "$r6","$r7"
push_fpu
.endm
.macro SYSCALL_RESTORE_ALL
pop_fpu
lwi $sp, [$sp] ! restore align_sp_8
popm $r6, $r7 ! restore $ipc, $ipsw
mtsr $r6, $IPC
mtsr $r7, $IPSW
pop_ifc_lp "$r6"
pop_d0d1 "$r6","$r7","$r8","$r9"
popm $r15,$r30
popm $r1, $r9
.endm
.macro SAVE_ALL_HW0
pushm $r0, $r5
pushm $r15,$r30
push_d0d1
push_ifc_lp
align_sp_8
push_fpu
.endm
.macro RESTORE_ALL_HW0
pop_fpu
lwi $sp, [$sp]
pop_ifc_lp
pop_d0d1
popm $r15,$r30
popm $r0, $r5
.endm
.macro SAVE_ALL_HW !should not touch $r0
/* push caller-saved gpr */
pushm $r1, $r5
pushm $r15, $r30
push_d0d1
push_ifc_lp
#if !(defined(NDS32_BASELINE_V3M) || defined(NDS32_BASELINE_V3))
/* push $INT_MASK */
mfsr $r1, $INT_MASK
push $r1 ! push $INT_MASK
/* disable low priority and
* enable high priority interrupt */
ori $r1, $r1, 0x3f ! r1= {mask[31:6],000000}
li $r2, 1
sll $r2, $r2, $r0 ! 1<